Active rectifier with delay locked loop to compensate for reverse current leakage and wireless power receiving apparatus including active rectifier with delay locked loop to compensate for reverse current leakage

An active rectifier comprising:

• a first circuit configured to provide a first voltage when a phase of an input signal is positive;
• and
• a second circuit configured to provide a second voltage when the phase of the input signal is negative,
• wherein the first circuit comprises:
• a switch configured to be turned on when the phase of the input signal is positive, based on a differential signal with respect to the input signal,
• a delay switch to be turned on when the phase of the input signal is positive, based on the differential signal with respect to the input signal,
• a first delay locked loop configured to compensate for a reverse current leakage due to a delay of a switch, between when a phase of a differential signal is switched from positive to negative and when the first delay switch is turned on, by adding a first voltage offset to the phase of the differential signal, and
• a first capacitor configured to provide a voltage corresponding to substantially a maximum amplitude of the input signal,
• wherein the delay switch comprises:
• a comparator configured to receive the differential signal and to output a predetermined voltage when the phase of the differential signal is negative;
• a voltage buffer configured to store the predetermined voltage outputted from the comparator, and, when the stored voltage becomes a turn-on voltage, to output the turn-on voltage;
• and
• a transistor configured to be turned on by the turn-on voltage outputted from the voltage buffer,
• wherein the delay locked circuit is configured to provide the first or second voltage offset corresponding to a second delay occurring due to the comparator and the voltage buffer, and to add the first or second voltage offset to the phase of the differential signal inputted to the comparator, and
• wherein the second circuit comprises:
• a second delay locked loop configured to compensate for a reverse current leakage due to a delay of a switch, between when the phase of the input signal is switched from positive to negative and when a second delay switch is turned on, by adding a second voltage offset to the phase of the input signal, and
• a second capacitor configured to provide a voltage corresponding to substantially a maximum amplitude of the input signal.

An active rectifier comprising:

• a first loop configured to provide a first voltage when the phase of an input signal is positive;
• and a second loop, separate and distinct from the first loop, configured to provide a second voltage when the phase of the input signal is negative, wherein the first loop comprises:
• a first switch configured to be turned on when the phase of the input signal is positive, based on a differential signal with respect to the input signal, a first delay switch to be turned on when the phase of the input signal is positive, based on the differential signal with respect to the input signal, and a capacitor configured to provide a voltage corresponding to substantially a maximum amplitude of the input signal, wherein the first delay switch comprises:
• a comparator configured to receive the differential signal and to output a predetermined voltage when the phase of the differential signal is negative;
• a voltage buffer configured to store the predetermined voltage outputted from the comparator, and, when the stored voltage becomes a turn-on voltage, to output the turn-on voltage;
• and a transistor configured to be turned on by the turn-on voltage outputted from the voltage buffer, wherein the first loop comprises a first delay locked loop configured to compensate for a reverse current leakage due to a delay of the transistor and provide the first voltage offset corresponding to a second delay occurring due to the comparator and the voltage buffer, and to add the first voltage offset to the phase of the differential signal inputted to the comparator, and wherein the second loop comprises a second delay locked loop configured to compensate for a reverse current leakage due to a delay of a switch, between when the phase of the input signal is switched from positive to negative and when a second delay switch is turned on, by adding a second voltage offset to the phase of the input signal.