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US 9,431,533 B2Granted
Method to enable higher carbon co-implants to improve device mismatch without degrading leakage
AssigneeTexas Instruments Incorporated
InventorEbenezer Eshun
Life of this patent
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Abstract
An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least one of the angled carbon co-implant is greater than the implant energy of the boron halo implant. A total carbon dose of the angled carbon co-implants is at least 5 times a total boron dose of the boron halo implants. The NMOS transistor has a carbon concentration in the halo regions which is at least 5 times greater than the boron concentration in the halo regions. The co-implanted carbon extends under the gate of the NMOS transistor.
Claims20
An integrated circuit, comprising:
- a substrate comprising a p-type semiconductor material, the semiconductor material being primarily silicon;
- a gate dielectric layer of an n-channel metal oxide semiconductor (NMOS) transistor disposed at a top surface of the p-type semiconductor material;
- a gate of the NMOS transistor disposed on the gate dielectric layer;
- a first carbon-diffused region disposed in the substrate adjacent to the gate, and extending a first distance under the gate, on a drain side of the gate and on a source side of the gate;
- a second carbon-diffused region disposed in the substrate adjacent to the gate, on the drain side of the gate and on the source side of the gate, and extending a second distance under the gate, the second distance being greater than the first distance;
- a halo region doped with boron disposed in the substrate adjacent to the gate, on the drain side of the gate and on the source side of the gate, and extending a third distance under the gate, the third distance being greater than the first distance;
- and
- a third carbon-diffused region disposed in the substrate adjacent to the gate, on the drain side of the gate and on the source side of the gate, and extending a fourth distance under the gate, the fourth distance being greater than the third distance, wherein a total amount of carbon in the first carbon-diffused region, the second carbon-diffused region and the third carbon-diffused region is at least 5 times a total amount of boron in the halo region.
5 more elements
A method of forming an integrated circuit, comprising the steps:
- providing a substrate comprising a p-type semiconductor material, the semiconductor material being primarily silicon;
- forming a gate dielectric layer of an NMOS transistor at a top surface of the p-type semiconductor material;
- forming a gate of the NMOS transistor on the gate dielectric layer;
- implanting a first dose of carbon into the substrate adjacent to the gate, with a first tilt angle greater than 15 degrees;
- implanting a second dose of carbon into the substrate adjacent to the gate, with a second tilt angle greater than 15 degrees, and with an energy 2 kilo-electron volts (keV) to 4 keV higher than an energy of the first dose of carbon;
- implanting a third dose of carbon into the substrate adjacent to the gate, with a third tilt angle greater than 15 degrees and with an energy 2 keV to 4 keV higher than an energy of the second dose of carbon;
- implanting boron dopants into the substrate adjacent to the gate, with a halo tilt angle greater than 15 degrees, and with an energy 2 keV to 4 keV less than the energy of the third dose of carbon, wherein the first tilt angle, the second tilt angle and the third tilt angle are each within 5 degrees of the halo tilt angle, and wherein a combined total carbon dose of the first dose of carbon, the second dose of carbon and the third dose of carbon is at least 5 times a total boron dose;
- and
- subsequently annealing the top surface of the substrate by heating to a temperature above 1200° C. for 1 microsecond to 1 millisecond.
6 more elements
A method of forming an integrated circuit, comprising the steps:
- providing a substrate comprising a p-type semiconductor material, the semiconductor material being primarily silicon;
- forming a gate dielectric layer of an NMOS transistor at a top surface of the p-type semiconductor material;
- forming a gate of the NMOS transistor with a physical gate length less than 30 nanometers on the gate dielectric layer;
- implanting a first dose of carbon into the substrate adjacent to the gate, with a first tilt angle;
- implanting a second dose of carbon into the substrate adjacent to the gate, with a second tilt angle, and with an energy 2 keV to 4 keV higher than an energy of the first dose of carbon;
- implanting a third dose of carbon into the substrate adjacent to the gate, with a third tilt angle, and with an energy 2 keV to 4 keV higher than an energy of the second dose of carbon;
- implanting a fourth dose of carbon into the substrate adjacent to the gate, with a fourth tilt angle less than 4 degrees;
- subsequently implanting boron dopants in the form of BF2 into the substrate adjacent to the gate, with a halo tilt angle of about 25 degrees to about 30 degrees, and with an energy 2 keV to 4 keV less than the energy of the third dose of carbon, wherein the first tilt angle, the second tilt angle and the third tilt angle are substantially equal to the halo tilt angle, and wherein a combined total carbon dose of the first dose of carbon, the second dose of carbon and the third dose of carbon is at least 5 times a total boron dose;
- and
- subsequently annealing the top surface of the substrate by heating to a temperature above 1200° C. for 1 microsecond to 1 millisecond by a scanned laser anneal process.
7 more elements
Dependencies are inferred from the claim text.