Patterning of vertical nanowire transistor channel and gate with directed self assembly

A method of forming a nanowire transistor on a substrate, the method comprising:

• forming a guide opening in a mask layer disposed over a dielectric layer disposed over a doped semiconductor layer disposed over a substrate;
• depositing a directed self-assembly (DSA) material into the guide opening;
• segregating the DSA material into an interior polymer region completely surrounded by an exterior polymer region within the guide opening, the interior polymer region having a cylindrical geometry having a diameter;
• removing the interior polymer region selectively to the exterior polymer region;
• forming a trench in the dielectric layer and the doped semiconductor layer wherein the trench has a diameter defined by the diameter of the cylindrical geometry of the interior polymer region;
• removing the mask layer and a peripheral portion of the dielectric layer beneath the mask layer to form an annular portion of the dielectric layer surrounding the trench;
• removing the exterior polymer region;
• depositing a first source/drain semiconductor material in the trench;
• depositing a channel semiconductor material on the first source/drain semiconductor material in the trench;
• depositing a second source/drain semiconductor material on the channel semiconductor material in the trench;
• removing at least a portion of the annular portion of the dielectric layer surrounding the trench to form a gate trench surrounding the channel semiconductor material;
• depositing a gate dielectric in the gate trench adjacent to and surrounding the channel semiconductor material;
• and
• depositing a gate electrode in the gate trench adjacent the gate dielectric layer in the gate trench and surrounding the channel semiconductor material.