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US 9,431,508 B2Granted
Simplified gate-first HKMG manufacturing flow
AssigneeGlobalfoundries Inc.
InventorsStefan Flachowsky, Jan Hoentschel, Roman Boschke
Life of this patent
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Abstract
When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.
Claims24
A method, comprising:
- forming an active region in a semiconductor layer of a semiconductor substrate;
- forming a gate structure of a transistor above said active region, said gate structure comprising;
- an HKMG material stack, comprising:
- a gate metal layer;
- and
- a conductive etch-stop layer formed above and conductively coupled to said gate metal layer;
- a gate electrode material formed above said conductive etch-stop layer of said HKMG material stack;
- and
- a gate cap layer formed above said gate electrode material;
- after forming said gate structure, forming a sidewall spacer structure adjacent to sidewalls of said gate structure, said sidewall spacer structure laterally confining sidewall surfaces of said HKMG material stack, said gate electrode material, and said gate cap layer;
- forming source and drain regions of said transistor in said active region;
- forming a dielectric material above said transistor, said dielectric material covering at least an upper surface of said gate cap layer;
- and
- forming a contact opening that extends through said dielectric material, said gate cap layer, and said gate electrode material so as to expose a first upper surface portion of said HKMG material stack and inside sidewalls of said gate electrode material while said gate electrode material covers a remaining upper surface portion of said HKMG material stack.
11 more elements
A method, comprising:
- forming a gate material stack above an active region formed in a semiconductor layer of a semiconductor substrate, said gate material stack comprising:
- a layer of gate insulation material;
- a layer of metal gate material formed above said layer of gate insulation material;
- a layer of conductive etch-stop material formed above said layer of metal gate material;
- a layer of gate electrode material formed above said layer of conductive etch-stop material;
- and
- a layer of dielectric cap material formed above said layer of gate electrode material;
- patterning a gate structure from said gate material stack during a common gate patterning process, said gate structure comprising:
- a gate insulation layer comprising said layer of gate insulation material;
- a gate metal layer positioned above said gate insulation layer and comprising said layer of metal gate material;
- a conductive etch-stop layer positioned above said gate metal layer and comprising said layer of conductive etch-stop material;
- a gate electrode layer positioned above said conductive etch-stop layer and comprising said layer of gate electrode material;
- and
- a cap layer positioned above said gate electrode layer and comprising said layer of dielectric cap material;
- after patterning said gate structure, forming a layer of stressed dielectric material above said transistor, said layer of stressed dielectric material covering at least said gate structure and an upper surface of said active region;
- forming a contact opening extending through said layer of stressed dielectric material, said cap layer, and said gate electrode layer, wherein said contact opening exposes a first upper surface portion of said conductive etch-stop layer and said gate electrode layer covers a remaining upper surface portion of said conductive etch-stop layer;
- and
- forming a conductive contact element in said contact opening, wherein a bottom surface of said conductive contact element directly contacts said first upper surface portion of said conductive etch-stop layer and sidewall surfaces of said contact element directly contact said gate electrode layer.
15 more elements
A method, comprising:
- forming an active region in a semiconductor layer of a semiconductor substrate;
- forming a gate structure of a transistor above said active region, said gate structure comprising:
- a gate insulation layer;
- a gate metal layer formed above said gate insulation layer;
- a conductive etch-stop layer formed above said gate metal layer;
- a gate electrode material formed above said conductive etch-stop layer;
- and
- a dielectric cap layer formed above said gate electrode material;
- after forming said gate structure, forming a sidewall spacer structure adjacent to sidewalls of said gate structure, said sidewall spacer structure laterally confining sidewall surfaces of at least said gate insulation layer, said gate metal layer, said conductive etch stop layer, and said gate electrode material;
- forming source and drain regions in said active region and laterally adjacent to said gate structure;
- forming an interlayer dielectric material above said transistor, said interlayer dielectric material covering said gate structure and an upper surface of said drain and source region;
- forming a patterned mask layer above said interlayer dielectric material;
- and
- performing an etching process through said patterned mask layer to form at least one contact opening that extends through at least said interlayer dielectric material, said cap layer, and said gate electrode material, said conductive etch-stop layer being used as an etch stop during said etching process, wherein after forming said at least one contact opening a first portion of said gate electrode material is exposed by sidewalls of said at least one contact opening, a second portion said gate electrode material covers an upper surface portion of said conductive etch-stop layer, and said conductive etch-stop layer covers an entire upper surface of said gate metal layer.
11 more elements
Dependencies are inferred from the claim text.