Replacement gate structure with low-K sidewall spacer for semiconductor devices
AssigneeGlobalfoundries Inc.
InventorsRuilong Xie, Kisik Choi
Life of this patent
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Abstract
One method and device disclosed includes, among other things, forming a recessed sacrificial gate electrode having a recessed upper surface, performing at least one second etching process to define recessed sidewall spacers positioned adjacent the recessed sacrificial gate electrode, forming a plurality of sidewall spacers within a gate opening above the recessed sidewall spacers, wherein one of the spacers comprises a low-k insulating material that is positioned laterally between two other spacers and a gate cap layer, removing the recessed sacrificial gate electrode and forming a replacement gate structure in its place.
Claims22
A device, comprising:
- a gate structure positioned above an upper surface of a semiconductor substrate, said gate structure comprising a high-k gate insulation layer (k value of 10 or greater) and a gate electrode comprised of at least one layer of metal;
- a lower sidewall spacer positioned adjacent opposite sides of at least a portion of said gate electrode, said lower sidewall spacers having an upper surface that is positioned above said upper surface of said substrate;
- a gate cap layer positioned above at least said gate electrode;
- a layer of insulating material positioned above said surface of said substrate and around said gate structure;
- and
- a plurality of sidewall spacers positioned laterally between said layer of insulating material and a portion of said gate structure and vertically between said upper surface of said lower sidewall spacer and a bottom surface of said gate cap layer, wherein said plurality of sidewall spacers comprise a low-k spacer comprised of an insulating material having a dielectric constant equal to or less than 3.9.
A device, comprising:
- a gate structure positioned above an upper surface of a semiconductor substrate, said gate structure comprising a high-k gate insulation layer (k value of 10 or greater) and a gate electrode comprised of at least one layer of metal;
- a lower sidewall spacer positioned adjacent opposite sides of at least a portion of said gate electrode, said lower sidewall spacer having an upper surface that is positioned above said upper surface of said substrate;
- a gate cap layer positioned above at least said gate electrode;
- a layer of insulating material positioned above said surface of said substrate;
- and
- a plurality of sidewall spacers positioned laterally between said layer of insulating material and a portion of said gate structure and vertically between said upper surface of said lower sidewall spacers and a bottom surface of said gate cap layer, wherein said plurality of spacers comprises:
- a first sidewall spacer positioned on said layer of insulating material;
- a second sidewall spacer positioned on said first sidewall spacer, said second sidewall spacer being comprised of an insulating material having a dielectric constant equal to or less than 3.9;
- and
- a third sidewall spacer positioned on said second sidewall spacer, wherein said first sidewall spacer and said third sidewall spacer are each comprised of a material having a dielectric constant of 5.5 or greater.
A device, comprising:
- a gate structure positioned above an upper surface of a semiconductor substrate, said gate structure comprising a high-k gate insulation layer (k value of 10 or greater) and a gate electrode comprised of at least one layer of metal;
- a lower sidewall spacer positioned adjacent opposite sides of at least a portion of said gate electrode, said lower sidewall spacer having an upper surface that is positioned above said upper surface of said substrate;
- a gate cap layer positioned above at least said gate electrode;
- a layer of insulating material positioned above said upper surface of said substrate;
- and
- a low-k spacer positioned laterally between said layer of insulating material and a portion of said gate structure and vertically between said upper surface of said lower sidewall spacer and a bottom surface of said gate cap layer, wherein said low-k spacer is comprised of an insulating material having a dielectric constant equal to or less than 3.9.
Dependencies are inferred from the claim text.