Integrating transistors with different poly-silicon heights on the same die

An integrated circuit, comprising:

• at least one first poly-silicon gate region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a plurality of first poly-silicon fingers associated with the first poly-silicon layer, and at least one second poly-silicon finger associated with the second poly-silicon layer, wherein the plurality of first poly-silicon fingers and the at least one second poly-silicon finger are orientated in a substantially orthogonal manner relative to each other;
• and wherein a gap between adjacent ones of the first poly-silicon fingers is filled with silicon oxide having a same thickness as a thickness of the first poly-silicon fingers;
• and at least one second poly-silicon gate region including the first poly-silicon layer, wherein the at least one first poly-silicon gate region and the at least one second poly-silicon gate region each have different poly-silicon gate structures.