Method of manufacturing a stress-controlled HEMT
AssigneeInfineon Technologies Austria AG
InventorsRalf Siemieniec, Gilberto Curatola
Life of this patent
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Abstract
A method of manufacturing a semiconductor device includes providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions, and forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material.
Claims15
A method of manufacturing a semiconductor device, the method comprising:
- providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions;
- and
- forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material, wherein the heterostructure body has a built-in stress induced by lattice mismatch between different layers of the heterostructure body, and wherein the piezoelectric material is formed on the heterostructure body with an orientation that counteracts the built-in stress in the heterostructure body so that the channel is disrupted below the piezoelectric material absent a voltage applied to the piezoelectric material.
A method of manufacturing a semiconductor device, the method comprising:
- providing a heterostructure body with a first doped region, a second doped region spaced apart from the first doped region and a two-dimensional charge carrier gas channel between the first and second doped regions;
- and
- forming a gate structure on the heterostructure body for controlling the channel, the gate structure comprising a piezoelectric material and an electrical conductor in contact with the piezoelectric material, wherein the gate structure is configured to control the channel below the piezoelectric material such that:
- (a) the two-dimensional charge carrier gas channel is uninterrupted below the piezoelectric material absent a voltage applied to the piezoelectric material;
- and
- (b) the piezoelectric material generates a force in response to a voltage applied to the piezoelectric material, the force being transferred to the heterostructure body to disrupt the two-dimensional charge carrier gas channel below the piezoelectric material.
Dependencies are inferred from the claim text.