Transistor devices having an anti-fuse configuration and methods of forming the same

A transistor device having an anti-fuse configuration, the transistor device comprising:

• a semiconductor substrate comprising a first fin and a second fin;
• a first insulator layer overlying the semiconductor substrate and having a thickness less than a height of the first fin and the second fin, with the first fin and the second fin extending through and protruding beyond the first insulator layer to provide buried fin portions embedded within the first insulator layer and exposed fin portions protruding beyond the first insulator layer;
• a gate electrode structure overlying the exposed fin portions of the first fin and the second fin, wherein the gate electrode structure wraps around the exposed fin portions of the first fin and the second fin on three sides thereof;
• and
• gate insulating structures disposed between the first fin and the gate electrode structure and between the second fin and the gate electrode structure, wherein the gate insulating structures comprise a first dielectric layer comprising a breakdown dielectric material overlying a first side of the respective fins and a second dielectric layer different from the first dielectric layer overlying a second side of the respective fins, wherein the first dielectric layer is thinner than the second dielectric layer to provide a potential breakdown path between the respective fins and the gate electrode structure through the first dielectric layer with the second dielectric layer absent from the potential breakdown path defined between the respective fins and the gate electrode structure through the first dielectric layer, and wherein the gate electrode structure is disposed over the first dielectric layer and the second dielectric layer, which insulate the first fin and the second fin from the gate electrode structure;
• wherein the second dielectric layer of the first fin and the second dielectric layer of the second fin are physically separate and spaced from each other with the gate electrode structure sandwiched therebetween.

A method of forming a transistor device having an anti-fuse configuration, the method comprising:

• providing a semiconductor substrate comprising a first fin and a second fin extending parallel to the first fin;
• depositing a first insulator material overlying the semiconductor substrate;
• etching the first insulator material to form a first insulator layer having a thickness less than a height of the first fin and the second fin, with the first fin and the second fin extending through and protruding beyond the first insulator layer to provide buried fin portions embedded within the first insulator layer and exposed fin portions protruding beyond the first insulator layer;
• forming a first dielectric layer comprising a breakdown dielectric material over a first surface of the first fin and the second fin;
• forming a second dielectric layer over a second surface of the first fin and a second surface of the second fin, wherein the second dielectric layer is different from the first dielectric layer;
• and
• forming a gate electrode structure over the first dielectric layer and the second dielectric layer wherein the gate electrode structure wraps around the exposed fin portion of the first fin and the exposed fin portion of the second fin on three sides thereof, with a potential breakdown path defined between the first fin and the gate electrode structure through the first dielectric layer and with the gate electrode structure disposed over the first dielectric layer and the second dielectric layer, which insulate the first fin from the gate electrode structure,
• wherein the second dielectric layer of the first fin and the second dielectric layer of the second fin are physically separate and spaced from each other with the gate electrode structure disposed therebetween.