Method of forming SGT MOSFETs with improved termination breakdown voltage
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsYongping Ding, Yeeheng Lee, Xiaobin Wang, Madhur Bobde
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AssigneeAlpha and Omega Semiconductor Incorporated
InventorsYongping Ding, Yeeheng Lee, Xiaobin Wang, Madhur Bobde
Estimating the term…
A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the termination trench and performing a second etching to increase the depth of the active trench to a desired depth wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller than a depth difference between the initial depth of the active trench and the desired depth of the termination trench.
A method for preparing a trench power semiconductor device comprising:
Dependencies are inferred from the claim text.