Diluted drift layer with variable stripe widths for power transistors

An integrated circuit (IC), comprising:

• a substrate doped a first dopant type;
• a multi-finger lateral high voltage transistor (MFLHVT), comprising:
• a stack on said substrate including a well doped a second dopant type, a buried drift layer (BDL) doped said first dopant type having a diluted BDL portion (DBDL) including a plurality of dilution stripes, a semiconductor surface on said BDL doped said second dopant type,
• dielectric isolation regions at least partially in said semiconductor surface having gaps defining a first active area in a first dielectric gap region (first MOAT) and a second active area in a second dielectric gap region (second MOAT);
• a drain comprising a plurality of drain fingers having drain fingertips in said second MOAT interdigitated with a source comprising a plurality of source fingers having source fingertips in said first MOAT each doped said second dopant type;
• a fingertip drift region (FDR) associated with at least one of said drain fingertips (drain FDR) and said source fingertips (source FDR) between said first MOAT and said second MOAT that said DBDL is within;
• an upper current channel in said semiconductor surface and lower current channel in said well both between said source and said drain;
• at least a first gate stack on said semiconductor surface between said source and said drain;
• wherein said plurality of dilution stripes have respective stripe widths that increase monotonically with a drift length at their respective positions, and
• a symmetric p-channel Metal Oxide Semiconductor (PMOS) transistor and symmetric n-channel MOS (NMOS) transistor formed in said substrate.