Back-end processing using low-moisture content oxide cap layer

A method for fabricating a semiconductor integrated circuit, the method comprising:

• generating front-end structures including one or more doped diffusion regions disposed in a semiconductor substrate, one or more polycrystalline silicon structures disposed over a surface of the substrate, and a pre-metal dielectric layer over the one or more polycrystalline silicon structures;
• forming a plurality of metallization layers over the pre-metal dielectric layer, wherein forming at least one of said metallization layers includes:
• forming a patterned metal structure;
• forming an interlevel dielectric (ILD) layer comprising a TEOS-based oxide over the patterned metal structure;
• and
• forming a cap layer over the ILD layer,
• wherein forming the cap layer comprises forming a high-density, low-moisture content oxide material having a minimum thickness of 100 A,
• wherein said semiconductor integrated circuit comprises an array of image sensing pixels disposed inside a rectangular imaging region of said semiconductor substrate, and
• wherein forming said patterned metal structure of at least one of said plurality of metallization layers comprises forming functional patterned aluminum structures over an interior of said rectangular imaging region, and forming non-functional patterned aluminum structures over an exterior peripheral region surrounding said rectangular imaging region.

An image sensor comprising:

• a semiconductor substrate including a plurality of doped diffusion regions disposed below an upper substrate surface;
• a plurality of polycrystalline silicon structures disposed on the semiconductor substrate over the upper substrate surface;
• a pre-metal dielectric layer formed over the polycrystalline silicon structures;
• and
• a back-end metallization structure formed on the pre-metal dielectric layer, the back-end metallization structure including a plurality of metallization layers formed in a stack, each of the metallization layers including a patterned aluminum layer and an interlevel dielectric (ILD) layer comprising TEOS-based oxide that is formed over the patterned aluminum layer,
• wherein at least one of the plurality of metallization layers includes a cap layer formed on the ILD layer, and
• wherein the cap layer of all of said plurality of metallization layers except an uppermost said metallization layer comprises a silane oxide layer having a minimum thickness of 100 A.