Thin film transistor array panel including layered line structure and method for manufacturing the same
AssigneeSamsung Display Co., Ltd.
InventorsJe Hun Lee, Yang Ho Bae, Beom-Seok Cho, Chang Oh Jeong
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Abstract
The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
Claims8
A thin film transistor array panel comprising:
- an insulating substrate;
- a gate line comprising a gate electrode and a data line comprising a source electrode, the gate line and the data line being disposed on the insulating substrate and insulated from each other to cross each other;
- an oxide semiconductor which is disposed on the insulating substrate;
- a gate insulating layer which is disposed between the gate line and the oxide semiconductor;
- a drain electrode adjacent to the source electrode and spaced apart therefrom;
- wherein at least one of the gate line, the data line, and the drain electrode comprises a first layer comprising a conductive oxide, a second layer comprising copper (Cu) and a third layer comprising a conductive oxide.
Dependencies are inferred from the claim text.