Method for creating metal gate resistor in FDSOL and resulting device

A method comprising:

• providing a silicon on insulator (SOI) stack including a silicon (Si) substrate, an insulator layer on an upper surface of the Si substrate, and a Si layer on an upper surface of the insulator layer;
• forming shallow trench isolation (STI) regions in the SOI stack at first, second, third, and fourth sides of a rectangular active area of the Si layer, the first side opposing the third and the second side opposing the fourth, wherein the STI regions extend vertically from an upper surface of the Si layer and into the Si substrate;
• recessing the STI regions, by a dry or wet etching process, below the upper surface of the insulator layer;
• undercutting the active area of the Si layer by an isotropic etching process, forming channels in the insulator layer along and under perimeter edges of the active area;
• conformally forming a high-k dielectric layer on all exposed surfaces;
• forming a metal layer on the high-k dielectric layer and filling the channels;
• removing the metal layer, by an anisotropic etching process, except for the filled channels and a portion over each of the STI regions at the first and third sides and overlapping the active area;
• and
• forming low-k spacers on exposed opposing sidewalls of the metal portions overlapping the active area, exposed vertical surfaces of the high-k dielectric layer on edges of the active area, and exposed surface of the filled channels.