Data line arrangement and pillar arrangement in apparatuses

An apparatus, comprising a plurality of semiconductor pillars in a substantially hexagonally closest packed arrangement;

• the hexagonally closest packed arrangement comprising a repeating pillar pattern, with the repeating pillar pattern having at least portions of 7 different pillars, wherein each of the different pillars in a respective one of the repeating pillar patterns is electrically coupled to a different data line of a plurality of data lines;
• wherein the data lines are on a pitch of less than or equal to about 60 nanometers;
• wherein each of the pillars in a respective one of the repeating pillar patterns is encompassed by a single drain-side select gate (SGD) of a plurality of SGDs, and wherein the SGDs are on a pitch of greater than or equal to about 400 nanometers;
• wherein the pillars and SGD are supported by a base comprising monocrystalline silicon;
• and wherein the pillars comprise polysilicon surrounding dielectric material.