Semiconductor devices including vertical cell strings that are commonly connected
AssigneeSamsung Electronics Co., Ltd.
InventorSung-Min Hwang
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes bit lines on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel structures connecting the bit lines to the common source line. Each of the channel structures may include a plurality of first vertical portions penetrating the gate structure and being connected to the bit lines, a second vertical portion penetrating the gate structure and being connected to the common source line, and a horizontal portion provided between the substrate and the gate structure to connect the first and second vertical portions to each other.
Claims17
A semiconductor device, comprising:
- bit lines on a substrate;
- a gate structure between the substrate and the bit lines;
- a common source line between the gate structure and the bit lines;
- and
- channel structures connecting the bit lines to the common source line,
- wherein each of the channel structures comprises:
- first vertical portions penetrating the gate structure and being connected to the bit lines;
- a second vertical portion penetrating the gate structure and being connected to the common source line;
- and
- a horizontal portion between the substrate and the gate structure to connect the first and second vertical portions to each other,
- wherein the common source line comprises a first common source line and a second common source line spaced apart from each other, and
- the second vertical portion of each of the channel structures comprises a pair of second vertical portions coupled to the first and second common source lines, respectively.
A semiconductor device comprising:
- a substrate;
- first, second and third strings of nonvolatile memory cells that are stacked on the substrate and spaced apart from each other, such that the first, second and third strings of nonvolatile memory cells each comprises a first end adjacent the substrate and a second end remote from the substrate;
- first, second and third conductive lines, a respective one of which is connected to a respective second end of the first, second and third strings of nonvolatile memory cells;
- and
- a fourth conductive line that connects the first ends of the first, second and third strings of nonvolatile memory cells in common,
- wherein the first and third strings of memory cells each further comprises a string selection transistor and is devoid of a ground selection transistor and wherein the second string of memory cells comprises a ground selection transistor and is devoid of a string selection transistor.
A semiconductor device comprising:
- a substrate;
- first, second and third strings of nonvolatile memory cells that are stacked on the substrate and spaced apart from each other, such that the first, second and third strings of nonvolatile memory cells each comprises a first end adjacent the substrate and a second end remote from the substrate;
- first, second and third conductive lines, a respective one of which is connected to a respective second end of the first, second and third strings of nonvolatile memory cells;
- a fourth conductive line that connects the first ends of the first, second and third strings of nonvolatile memory cells in common;
- a fourth string of nonvolatile memory cells that are stacked on the substrate and are spaced apart from the first through third strings of nonvolatile memory cells, the fourth string of memory cells comprising a first end adjacent the substrate and a second end remote from the substrate;
- and
- a fifth conductive line that is connected to the second end of the fourth string of nonvolatile memory cells,
- wherein the fourth conductive line also connects the first end of the fourth string of nonvolatile memory cells in common to the first ends of the first, second and third strings of nonvolatile memory cells.
Dependencies are inferred from the claim text.