Vertical memory devices and methods of manufacturing the same

A vertical memory device, comprising:

• a plurality of channel arrays including a plurality of channels in a first region on a substrate, each of the channels extending in a first direction substantially perpendicular to a top surface of the substrate;
• a charge storage layer structure including a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern which are sequentially stacked on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate;
• and
• a plurality of gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction;
• wherein each channel array includes:
• a first channel column including a plurality of first channels disposed at a central portion of the first region with respect to a third direction substantially perpendicular to the first direction and the second direction;
• a second channel column including a plurality of second channels disposed at an outer portion of the first region, the second channels being spaced apart from respective first channels in a fourth direction oblique to the third direction;
• and
• a third channel column including a plurality of third channels disposed at the outer portion of the first region, the third channels being spaced apart from respective second channels in the second direction;
• a first conductive pattern electrically connecting a second channel of one channel array with a third channel of another channel array;
• and
• a second conductive pattern electrically connecting a third channel of the one channel array with a second channel of the other channel array;
• wherein a plurality of first conductive patterns is arranged in the third direction, and a plurality of second conductive patterns is arranged in the third direction;
• wherein a central portion of the first conductive pattern is curved in the third direction, and a central portion of the second conductive pattern is curved in a direction opposed to the third direction.

A vertical memory device, comprising:

• a plurality of channel arrays including a plurality of channels in a first region on a substrate, each of the channels extending in a first direction substantially perpendicular to a top surface of the substrate;
• a charge storage layer structure including a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern which are sequentially stacked on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate;
• and
• a plurality of gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction;
• wherein each channel array includes:
• a first channel column including a plurality of first channels disposed at a central portion of the first region with respect to a third direction substantially perpendicular to the first direction and the second direction;
• a second channel column including a plurality of second channels disposed at an outer portion of the first region, the second channels being spaced apart from respective first channels in a fourth direction oblique to the third direction;
• and
• a third channel column including a plurality of third channels disposed at the outer portion of the first region, the third channels being spaced apart from respective second channels in the second direction;
• a first conductive pattern electrically connecting a second channel of one channel array with a third channel of another channel array;
• a second conductive pattern electrically connecting a third channel of the one channel array with a second channel of the other channel array;
• and
• a plurality of first bit line, a plurality of second bit line and a plurality of third bit line electrically connected to respective channels;
• wherein the first bit lines are electrically connected to the first channels, the second bit lines are electrically connected to the second channels or the third channels through the first conductive patterns, and the third bit lines are electrically connected to the second channels or the third channels through the second conductive patterns;
• wherein the first bit lines overlap central portions of the first channels with respect to the first direction, the second bit lines overlap central portions of the first conductive patterns with respect to the first direction, and the third bit lines overlap central portions of the second conductive patterns with respect to the first direction.