STI recess method to embed NVM memory in HKMG replacement gate technology
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHarry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.
Claims18
An integrated circuit (IC), comprising:
- a semiconductor substrate having an upper substrate surface;
- a shallow trench isolation (STI) region made of a dielectric material disposed in the semiconductor substrate, wherein the STI region includes non-planar peripheral regions, which extend upward above the upper substrate surface, and also includes a central region, which is recessedly arranged between the non-planar peripheral regions;
- a conductive body which is arranged over the central region and which has a planar upper surface;
- and
- a contact which is ohmically coupled to the planar upper surface of the conductive body and which is arranged over the central region.
An integrated circuit (IC) for an embedded flash memory device, the IC comprising:
- a semiconductor substrate including a memory array region and a memory contact pad region;
- a pair of flash memory cells disposed above the memory array region;
- a memory gate contact structure disposed above the memory contact pad region;
- and
- a shallow trench isolation (STI) region disposed within the semiconductor substrate in the memory contact pad region, wherein an upper surface of the STI region comprises a planar central region and non-planar peripheral regions, and wherein the planar central region is substantially co-planar with an upper surface of the semiconductor substrate in the memory array region.
An integrated circuit (IC), comprising:
- a semiconductor substrate having an upper substrate surface;
- a shallow trench isolation (STI) region made of a dielectric material disposed in the semiconductor substrate, wherein the STI region includes non-planar peripheral regions, which extend upward above the upper substrate surface, and also includes a central region, which is recessedly arranged between the non-planar peripheral regions, and wherein vertical, substantially vertical or rounded sidewalls extend between the central region and upper portions of the non-planar peripheral regions;
- and
- a conductive body which is arranged directly on the central region of the STI region and which has a planar upper surface.
Dependencies are inferred from the claim text.