US 9,431,411 B1Granted

Efficient process for 3D NAND memory with socketed floating gate cells

AssigneeSanDisk Technologies LLC

InventorRaul Adrian Cernea

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Abstract

A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory layer each has a series of socket components aligned to embed respective floating gates of a group memory cells. This structure allows reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. The memory is fabricated by using odd and even subarrays of vertical shafts on a multi-layer slab to create at different times odd and even socket components that overlap to form continuous word lines with socket components. In particular, with only three masks, the even memory cells are fabricated to have their word line socket component enlarged to overlap with those of the odd memory cells in order to form continuous word lines in the row direction.

Claims20

Dependent claims

A method forming a 3D NAND memory, comprising:

(a) forming a multi-layer slab on top of a semiconductor substrate with layers corresponding to structures of an array of vertically aligned NAND strings, the layers including memory layers initially constituted from a sacrificial material;
(b) etching with a trench mask to form trenches spaced apart by ledges in the multi-layer slab;
(c) filling the trenches with the sacrificial material;
(d) providing odd and even masks for respectively providing subarrays of odd and even openings aligned within the trenches on top of the multi-layer slab;
(e) forming a subarray of odd vertical shafts by etching the sacrificial material through the odd openings anisotropically;
(f) forming odd grottoes by etching isotropically through the odd vertical shafts to recess the sacrificial material at the memory layers such that each odd grotto has walls intruding halfway into a respective adjacent ledge;
(g) depositing a layer of word line material in in the odd grottoes to form odd socket components of word lines;
(h) depositing a layer of insulating material to line each odd socket component;
(i) filling each odd socket component with a floating gate material to form an embedded floating gate;
(j) forming odd memory cells and a plurality of odd vertical bit lines through the odd vertical shafts;
and
(k) repeating (e)-(i) with “odd” and “even” interchanged, wherein said etching isotropically in (f) creates overlapping grottoes with adjoining walls between adjacent pairs of odd and even grottoes in the same memory layer to form a continuous word line with alternating first and second socket components in a row.

9 more elements

A method of forming a 3D NAND memory having memory cells arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions, said method comprising:

(a) forming a multi-layer slab on top of a semiconductor substrate in an x-y plane, layers of the multi-layer slab being stacked in the z-direction and corresponding to structures of an array in the x-y plane of vertically aligned NAND strings in the z-direction, the layers including memory layers initially constituted from a sacrificial material;
(b) etching with a trench mask to form trenches elongated in the x-direction and spaced apart in the y-direction by ledges in the multi-layer slab;
(c) filling the trenches with the sacrificial material;
(d) providing odd and even masks for respectively providing subarrays of odd and even openings aligned within the trenches on top of the multi-layer slab;
(e) forming a subarray of odd vertical shafts in the z-direction by etching the sacrificial material through the odd openings anisotropically;
(f) forming odd grottoes by etching isotropically through the odd vertical shafts to recess the sacrificial material at the memory layers such that each odd grotto has walls intruding in the x-y plane halfway into a respective adjacent ledge;
(g) depositing a layer of word line material in in the odd grottoes to form odd socket components of word lines;
(h) depositing a layer of insulating material to line each odd socket component;
(i) filling each odd socket component with a floating gate material to form an embedded floating gate;
(j) forming odd memory cells and a plurality of odd vertical bit lines through the odd vertical shafts;
and
(k) repeating (e)-(i) with “odd” and “even” interchanged, wherein said etching isotropically in (f) creates overlapping grottoes with adjoining walls between adjacent pairs of odd and even grottoes in the same memory layer to form a continuous word line with alternating first and second socket components in a row along the x-direction.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/825,408Filed 13 Aug 2015
Granted: 30 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10D 64/035
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures
H10D 64/661
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor comprising a layer of…