US 9,431,410 B2Granted

Methods and apparatuses having memory cells including a monolithic semiconductor channel

AssigneeMicron Technology, Inc.

InventorsJie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan

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Abstract

Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Claims11

Dependent claims

An apparatus comprising:

a vertical string of memory cells formed at least partially in a stack of materials comprising
a plurality of alternating levels of control gate material and insulator material,
wherein a memory cell of the string comprises:
a dielectric material in a recess formed in a level of the control gate material;
a charge storage structure in the recess adjacent to the dielectric material;
and tunnel dielectric material adjacent to the charge storage structure wherein the tunnel dielectric material is formed only in the recess over the charge store structure and is not formed over levels of the insulator material;
wherein a monolithic channel material of the vertical string of memory cells is adjacent to the tunnel dielectric material and extends adjacent to the plurality of alternating levels of control gate material and insulator material, the channel material having a thickness that is less than a width of a first opening through the alternating levels of control gate material and insulator material in which channel material is formed, such that a second opening is defined by the channel material and the channel material is monolithic with regard to having a single structure covering a sidewall and a bottom of the first opening;
a conductive plug formed in the second opening to connect the channel material;
and
a metal source coupled between the channel material and a substrate, wherein an oxide is formed between the metal source and the substrate.

7 more elements

A system comprising:

a controller;
and
a memory device coupled to the controller, the memory device comprising a memory array having a plurality of strings of memory cells, each string of memory cells of the plurality of strings of memory cells comprising:
a source select gate material over a metal source material, the metal source formed over a substrate wherein an oxide is formed between the metal source and the substrate;
a plurality of alternating levels of control gate and insulator materials over the source select gate material, each level of control gate material of the plurality of alternating levels of control gate and insulator materials having a charge storage structure formed in a recess in each level of control gate material;
and
a monolithic vertical channel material formed along a sidewall of a first opening through the plurality of alternating levels of control gate and insulator materials and the source select gate material, the vertical channel material coupled to the metal source material and being adjacent to the charge storage structures and the source select gate material, wherein the charge storage structures and the source select gate material are separated from the vertical channel material by at least a tunnel dielectric material, the vertical channel material having a thickness that is less than a width of the first opening, such that a second opening is defined by the vertical channel material, wherein the tunnel dielectric material is formed only in the recess over the charge store structure and is not formed over levels of the insulator material and further wherein the monolithic vertical channel material is monolithic with regard to having a single structure covering the sidewall and a bottom of the first opening;
and
a conductive plug formed at a top of the second opening to connect the vertical channel material.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/069,574Filed 1 Nov 2013
Published: US 2015/0123189 A17 May 2015
Granted: 30 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND