Method of making a three-dimensional memory array with etch stop

A three dimensional memory device, comprising:

• a substrate;
• a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of the substrate;
• at least one charge storage region located adjacent to the semiconductor channel;
• a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
• an etch stop layer located between the substrate and the plurality of control gate electrodes;
• a first insulating layer located between the etch stop layer and the substrate, or between the etch stop layer and the plurality of control gate electrodes:
• a trench extending through the plurality of control gate electrodes and extending vertically to a top surface of the etch stop layer, the top surface of the etch stop layer being a topmost surface or a recessed surface of the etch stop layer;
• and
• a material portion located in the trench and having a bottommost surface that contacts the top surface of the etch stop layer and continuously extending through the plurality of control gate electrodes and above a horizontal plane including a topmost surface of the plurality of control gate electrodes,
• wherein:
• the device comprises a vertical NAND string;
• the semiconductor channel has a U-shaped side cross section, comprising:
• two wing portions which extend substantially perpendicular to the major surface of the substrate through the etch stop layer, and
• a connecting portion which extends substantially parallel to the major surface of the substrate below the etch stop layer and which connects the two wing portions;
• the connecting portion of the semiconductor channel is located below an air gap trench which separates the two wing portions;
• and
• the connecting portion is located below the etch stop layer.

A monolithic, three dimensional array of memory devices located over a silicon substrate, comprising an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level, wherein at least one vertically oriented NAND string of the array of vertically oriented NAND strings comprises:

• a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a silicon substrate;
• at least one charge storage region located adjacent to the semiconductor channel;
• a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the silicon substrate and below the first device level;
• an etch stop layer located between the silicon substrate and the plurality of control gate electrodes;
• a first insulating layer located between the etch stop layer and the silicon substrate, or between the etch stop layer and the plurality of control gate electrodes;
• a trench extending through the plurality of control gate electrodes and extending vertically to a top surface of the etch stop layer, the top surface of the etch stop layer being a topmost surface or a recessed surface of the etch stop layer;
• and
• a material portion located in the trench and having a bottommost surface that contacts the top surface of the etch stop layer and continuously extending through the plurality of control gate electrodes and above a horizontal plane including a topmost surface of the plurality of control gate electrodes,
• wherein the semiconductor channel extends through the etch stop layer and the first insulating layer;
• and
• an integrated circuit comprising a driver circuit for the array of memory devices located on the silicon substrate.

A monolithic, three dimensional array of memory devices located over a silicon substrate, comprising an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level, wherein at least one vertically oriented NAND string of the array of vertically oriented NAND strings comprises:

• a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a silicon substrate;
• at least one charge storage region located adjacent to the semiconductor channel;
• a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the silicon substrate and below the first device level;
• an etch stop layer located between the silicon substrate and the plurality of control gate electrodes;
• a first insulating layer located between the etch stop layer and the silicon substrate, or between the etch stop layer and the plurality of control gate electrodes;
• a trench extending through the plurality of control gate electrodes and extending vertically to a top surface of the etch stop layer, the top surface of the etch stop layer being a topmost surface or a recessed surface of the etch stop layer;
• a material portion located in the trench and having a bottommost surface that contacts the top surface of the etch stop layer and continuously extending through the plurality of control gate electrodes and above a horizontal plane including a topmost surface of the plurality of control gate electrodes;
• and
• an integrated circuit comprising a driver circuit for the array of memory devices located on the silicon substrate,
• wherein:
• the semiconductor channel has a U-shaped side cross section, comprising:
• two wing portions which extend substantially perpendicular to the major surface of the substrate through the etch stop layer, and
• a connecting portion which extends substantially parallel to the major surface of the substrate below the etch stop layer and which connects the two wing portions;
• the connecting portion of the semiconductor channel is located below an air gap trench which separates the two wing portions;
• and
• the connecting portion is located below the etch stop layer.