Methods for fabricating integrated circuits with a high-voltage MOSFET

A method for fabricating an integrated circuit comprising:

• forming a first silicon material layer over a semiconductor substrate, the semiconductor substrate including a high-voltage MOSFET region, a logic device region, and a memory array region, the memory array region having formed on the semiconductor substrate a memory gate stack;
• forming a first capping layer over the first silicon material layer and over the memory gate stack;
• removing the first capping layer from over the memory array region but not from over the high-voltage MOSFET region and the logic device region of the integrated circuit;
• forming a second silicon material layer over the first capping layer and over the first silicon material layer;
• removing the second silicon material layer in an amount such that the second silicon material layer is completely removed from over the high-voltage MOSFET region and the logic device region;
• removing the first capping layer from over the first silicon material layer in the high-voltage MOSFET region and the logic device region;
• forming a second capping layer over the first silicon material layer in the high-voltage MOSFET region and the logic device region;
• removing the first silicon material layer and the second capping layer from the high-voltage MOSFET region except in an area overlying a channel region of the high-voltage MOSFET region.

A method for fabricating an integrated circuit comprising:

• depositing a first polysilicon layer over a semiconductor substrate, the semiconductor substrate including a high-voltage MOSFET region, a logic device region, and a memory array region, the memory array region having formed on the semiconductor substrate a floating-gate memory stack;
• depositing a silicon oxide first capping layer over the first polysilicon layer and over the memory gate stack;
• removing the first capping layer from over the memory array region but not from over the high-voltage MOSFET region and the logic device region of the integrated circuit;
• depositing a second polysilicon layer over the first capping layer and over the first polysilicon layer;
• removing, by a combination of chemical mechanical planarization and etching, the second polysilicon layer in an amount such that the second silicon material layer is completely removed from over the high-voltage MOSFET region and the logic device region;
• forming a second capping layer over the first silicon material layer in the high-voltage MOSFET region and the logic device region;
• removing the first silicon material layer and the second capping layer from the high-voltage MOSFET region except in an area overlying a channel region of the high-voltage MOSFET region;
• removing the first silicon material layer and the second capping layer from a word-line region of the memory array region;
• removing the first silicon material layer and the second capping layer from the logic device region except in an area overlying a channel region of the logic device region;
• depositing a photoresist material layer over the memory array region and the logic device region;
• and
• forming a lightly-doped drain (LDD) region in the high-voltage MOSFET region by exposing the semiconductor substrate to a dopant ion implantation process.