Semiconductor device and method of forming the same
AssigneeMacronix International Co., Ltd.
InventorsTing-Feng Liao, Yao-Fu Chan
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Abstract
A semiconductor device and a method of forming the same are provided. At least two separated stacked structures and at least two hard mask patterns respectively on the stacked structures are formed on a substrate. A patterned mask layer is formed on the substrate. The patterned mask layer has an opening which exposes a portion of top surfaces of the hard mask patterns and a portion of the substrate between the stacked structures. The exposed portion of the substrate is removed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a trench in the substrate. An ion implantation process is performed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a doped region in the substrate around the trench.
Claims10
A semiconductor device, comprising:
- a substrate;
- a plurality of stacked structures, located on the substrate, wherein the substrate has therein a trench between adjacent stacked structures, and each stacked structure comprises a floating gate, an inter-gate dielectric layer and a control gate sequentially located on the substrate;
- and
- a doped region, located in the substrate around the trench, wherein a volume ratio of a first portion to a second portion of the control gate is less than about 12%, an electrical conductivity of the first portion is lower than an electrical conductivity of the second portion, and the first portion is closer to a top corner of the trench than the second portion.
A semiconductor device, comprising:
- a substrate;
- a plurality of stacked structures, located on the substrate, wherein the substrate has a trench therein between adjacent stacked structures, wherein each stacked structure comprises a floating gate, an inter-gate dielectric layer and a control gate sequentially disposed on the substrate;
- and
- a doped region, located in the substrate around the trench, wherein an interface between polycrystalline silicon and amorphous silicon of the control gate and a bottom of the control gate define therebetween an acute angle of about 82 to 88 degrees.
Dependencies are inferred from the claim text.