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US 9,431,401 B2Granted
Memory device comprising electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsJin-Woo Han, Yuniarto Widjaja
Life of this patent
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Abstract
A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
Claims17
A semiconductor memory array comprising at least two memory cells, wherein each said memory cell comprises:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region;
- and
- a buried layer region located below said floating body region and said second insulating regions:
- wherein at least one of said floating body regions is integral with or connected to another of said floating body regions.
6 more elements
A semiconductor memory array comprising at least two memory cells, wherein each said memory cell comprises:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region;
- and
- a buried layer region located below said floating body region and said second insulating regions,
- wherein at least one of said floating body regions is integral with or connected to another of said floating body regions;
- and
- wherein a depletion region formed as a result of an application of a back bias to said buried layer region and at least one of said second insulating regions adjacent to said floating body region insulate said memory cell from an adjacent memory cell.
8 more elements
A semiconductor memory array comprising at least two memory cells, wherein each said memory cell comprises:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region;
- and
- a buried layer region located below said floating body region and said second insulating regions,
- wherein at least one of said floating body regions is integral with or connected to another of said floating body regions;
- wherein a depletion region formed as a result of an application of a back bias to said buried layer region and at least one of said second insulating regions adjacent to said floating body region insulate said memory cell from an adjacent memory cell, and
- wherein application of said back bias results in at least two stable floating body charge levels.
8 more elements
Dependencies are inferred from the claim text.