Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering

A semiconductor chip comprising:

• a circuit comprising
• a plurality of p channel field effect transistors wherein the p channel field effect transistors are connected in series and their gates are connected;
• a plurality of n channel field effect transistors wherein the n channel field effect transistors are connected in series and their gates are connected;
• a first power supply terminal configured to receive a first supply voltage with an upper supply potential;
• and
• a second power supply terminal configured to receive a second supply voltage with a lower supply potential;
• wherein the p channel field effect transistors and the n channel field effect transistors are connected such that
• the n channel field effect transistors, if supplied with the upper supply potential at their gates, supply the lower supply potential to the gates of the p channel field effect transistors;
• and
• the p channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gates of the n channel field effect transistors;
• wherein the circuit is configured such that the logic state of the gates of the p channel field effect transistors and the logic state of the gates of the n channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit;
• and
• a connection coupled to the gates of the p channel field effect transistors or the gates of the n channel field effect transistors and a further component of the semiconductor chip.