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US 9,431,397 B2Granted
Method for fabricating a multi-gate device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
Life of this patent
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Abstract
A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.
Claims19
A semiconductor device comprising:
- a substrate including an isolation feature;
- at least two fin structures embedded in the isolation feature;
- at least two gate stacks disposed around the at least two fin structures respectively;
- an etch stop layer extending between the at least two gate stacks;
- a first inter-layer dielectric (ILD) layer disposed on the etch stop layer and between the at least two gate stacks, wherein a portion of the first ILD layer has a top surface lower than a top surface of the at least two gate stacks, thereby forming a recess comprising a bottom surface and sidewall surfaces composed of the first ILD layer;
- and
- a second ILD layer disposed over the first ILD layer and in the recess, wherein the second ILD layer has a top surface that is approximately the same as the top surface of the at least two gate stacks and being contact with the sidewall surfaces and the bottom surface, wherein the second ILD layer disposed in the recess has a first thickness over the isolation feature and a second thickness adjacent one of the at least two gate stacks, the second thickness being different than the first thickness.
4 more elements
A device comprising:
- a first fin structure embedded in an isolation feature disposed within a semiconductor substrate;
- a first gate stack and a second gate stack disposed over the semiconductor substrate, wherein the first gate stack is disposed around the first fin structure;
- an etch stop layer extending between the first gate stack and the second gate stack;
- a first inter-layer dielectric (ILD) layer disposed between the first and second gate stacks and defining a recess having a bottom surface below a top surface of the first gate stack, the recess further includes sidewall surfaces such that the bottom surface and the sidewall surfaces are formed of the first ILD layer;
- and
- a second ILD layer disposed over the first ILD layer and in the recess such that the second ILD layer physically contacts the bottom surface and the sidewall surfaces, wherein the second ILD layer has a top surface that is coplanar with the top surface of the first gate stack, wherein the second ILD layer disposed in the recess has a first thickness over the isolation feature and a second thickness adjacent the first gate stack, the second thickness being different than the first thickness.
3 more elements
A device comprising:
- a first gate stack and a second gate stack disposed over a semiconductor substrate, wherein an isolation feature is disposed within the semiconductor substrate between the first gate stack and the second gate stack, the isolation feature defining a first active region and a second active region such that the first gate stack is over the first active region and the second gate stack is over the second active region;
- an etch stop layer having a first portion disposed along a first sidewall of the first gate stack and a second portion disposed along a second sidewall of the second gate stack;
- a first inter-layer dielectric (ILD) layer extending from the first portion of the etch stop layer disposed along the first sidewall to the second portion of the etch stop layer disposed along the second sidewall, wherein the first ILD layer defines a recess having a bottom surface below a top surface of the first gate stack, the recess further includes sidewall surfaces such that the bottom surface and the sidewall surfaces are formed of the first ILD layer;
- and
- a second ILD layer disposed over the first ILD layer and in the recess such that the second ILD layer physically contacts with the bottom surface and the sidewall surfaces, wherein the second ILD layer extends from the first portion of the etch stop layer disposed along the first sidewall to the second portion of the etch stop layer disposed along the second sidewall, wherein the second ILD layer has a top surface that is coplanar with the top surface of the first gate stack, wherein the second ILD layer disposed in the recess has a first thickness over the isolation feature and a second thickness adjacent the first gate stack, the second thickness being different than the first thickness.
2 more elements
Dependencies are inferred from the claim text.