Power semiconductor package with gate and field electrode leads

A power semiconductor package, comprising:

• a housing;
• a semiconductor chip embedded in the housing, the semiconductor chip comprising a first doping region in ohmic contact with a first metal layer arranged on a first side of the semiconductor chip, a second doping region in ohmic contact with a second metal layer arranged on a second side of the semiconductor chip that is opposite the first side, and a plurality of trenches formed in the semiconductor chip, wherein the trenches comprise gate electrodes and at least first field electrodes electrically insulated from the gate electrodes;
• and
• at least four terminals partially embedded in the housing and partially exposed to the outside of the housing, wherein
• a first terminal of the at least four terminals is electrically connected to the first metal layer,
• a second terminal of the at least four terminals is electrically connected to the second metal layer,
• a third terminal of the at least four terminals is electrically connected to the gate electrodes of the trenches, and
• a fourth terminal of the at least four terminals is electrically connected to the first field electrode of every nth numbered trench of the trenches, and electrically insulated from the first field electrodes of the other trenches, wherein n is equal to or larger than 2.