System and method of processing cutting layout and example switching circuit

A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC), comprising:

• receiving a layout including a gate electrode layout and a CUT layout, wherein the CUT layout includes a first CUT layout pattern and a second CUT layout pattern, and a space between the first CUT layout pattern and the second CUT layout pattern is less than a predetermined spatial resolution requirement;
• introducing a stitching layout pattern into the CUT layout, wherein the stitching layout connects the first CUT layout pattern and the second CUT layout pattern;
• merging the first CUT layout pattern, the second CUT layout pattern, and the stitching layout pattern;
• and
• adding a remedial connecting layout pattern to a first conductive layer of the gate electrode layout based on the stitching layout pattern, wherein at least one of the above operations is performed using an integrated circuit designing system comprising a processor.

A method of adjusting a layout usable for using a multiple patterning process of an integrated circuit, comprising:

• receiving a first set of layout patterns, each layout pattern of the first set of layout patterns extending along a first direction and having a first predetermined spatial resolution along a second direction transverse to the first direction;
• receiving a second set of layout patterns, each layout pattern of the second set of layout patterns corresponding to a conductive layer of the integrated circuit and having a second predetermined spatial resolution;
• generating a third set of layout patterns, the third set of layout patterns corresponding to a set of cutting patterns, each layout pattern of the third set of patterns orthogonally overlapping at least one layout pattern of the first set of layout patterns and having a third predetermined spatial resolution;
• generating a fourth set of layout patterns, the fourth set of layout patterns corresponding to a set of stitching patterns, each layout pattern of the fourth set of layout patterns overlapping at least one layout pattern of the first set of layout patterns;
• merging at least one layout pattern of the fourth set of layout patterns with two layout patterns of the third set of patterns;
• and
• generating a fifth set of layout patterns, the fifth set of layout patterns corresponding to a set of remedial connecting patterns, each layout pattern of the fifth set of layout patterns overlying at least one layout pattern of the third set of layout patterns, wherein the fifth set of layout patterns corresponds to the conductive layer of the integrated circuit, wherein at least one of the above operations is performed using an integrated circuit designing system comprising a processor.