Selective area heating for 3D chip stack

A method of forming a 3D package comprising a laminate chip carrier, an interposer, and a top chip, the method comprising:

• attaching a first plurality of solder bumps of the interposer to a first plurality of metallic contacts of the laminate chip carrier by applying a first selective non-uniform heat, a first selective non-uniform cooling, and a first uniform pressure to the first plurality of solder bumps, resulting in solid state diffusion of the first plurality of solder bumps into the first plurality of metallic contacts of the laminate chip carrier, wherein the first selective non-uniform heat is a temperature less than the reflow temperature of the first plurality of solder bumps;
• attaching a second plurality of solder bumps of the top chip to a second plurality of metallic contacts of the interposer by applying a second selective non-uniform heat, a second selective non-uniform cooling, and a second uniform pressure to the second plurality of solder bumps, resulting in solid state diffusion of the second plurality of solder bumps into the second plurality of metallic contacts of the interposer, wherein the second selective non-uniform heat is a temperature less than the reflow temperature of the second plurality of solder bumps;
• and
• heating the 3D package, the first plurality of solder bumps, and the second plurality of solder bumps to a temperature greater than the reflow temperature of the first plurality of solder bumps and the reflow temperature of the second plurality of solder bumps, wherein the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps.