# US 9,431,343 B1 · Stacked damascene structures for microelectronic devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,431,343 B1
- Document ID: US9431343B1
- Status: Granted
- Kind: B1
- Application number: 14/691,336
- Filed: 2015-04-20
- Published: 2016-09-15
- Granted: 2016-08-30
- Earliest claimed: 2015-03-11
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Ki-Don Lee; Jinseok Kim
- Inventors: Ki-Don Lee; Jinseok Kim
- Web page: https://patentgrep.com/patent/US9431343B1

## CPC

- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic device includes a dual-damascene interconnect structure and a single-damascene line structure directly on the dual-damascene interconnect structure. The dual-damascene interconnect structure and the single-damascene line structure may each include multiple line segments that are arranged in a brick wall pattern. The brick wall pattern may also be used with two or more single-damascene line structures. Various microelectronic devices and related fabrication methods are described.

## Claims

### Claim 1

A microelectronic device comprising:
a microelectronic substrate;
a dual-damascene interconnect structure on the microelectronic substrate, the dual-damascene interconnect structure comprising a conductive via and a first conductive line directly on the conductive via opposite the microelectronic substrate; and
a single-damascene line structure directly on the dual-damascene interconnect structure, the single-damascene line structure comprising a second conductive line on the first conductive line opposite the conductive via.

### Claim 2 (depends on 1)

The microelectronic device of claim 1:
wherein the dual-damascene interconnect structure further comprises a first barrier layer that extends on a bottom surface of the conductive via, on a sidewall of the conductive via, on a bottom surface of the first conductive line outside the conductive via and on a sidewall of the first conductive line, and
wherein the single-damascene line structure further comprises a second barrier layer that extends between a top surface of the first conductive line and a bottom surface of the second conductive line and on a sidewall of the second conductive line.

### Claim 3 (depends on 2)

The microelectronic device of claim 2 wherein the first barrier layer does not extend between the conductive via and the first conductive line.

### Claim 4 (depends on 1)

The microelectronic device of claim 1:
wherein the dual-damascene interconnect structure further comprises a first intermetal dielectric layer on the microelectronic substrate, wherein the first conductive line and the conductive via extend into the first intermetal dielectric layer, and
wherein the single-damascene line structure further comprises:
a second intermetal dielectric layer on the first intermetal dielectric layer opposite the substrate, wherein the second conductive line extends into the second intermetal dielectric layer; and
a capping layer between the first and second intermetal dielectric layers.

### Claim 5 (depends on 2)

The microelectronic device of claim 2:
wherein the dual-damascene interconnect structure further comprises a first intermetal dielectric layer on the microelectronic substrate, wherein the first conductive line, the conductive via and the first barrier layer extend into the first intermetal dielectric layer, and
wherein the single-damascene line structure further comprises:
a second intermetal dielectric layer on the first intermetal dielectric layer opposite the substrate, wherein the second conductive line extends into the second intermetal dielectric layer; and
a capping layer between the first and second intermetal dielectric layers, the capping layer being coplanar with a portion of the second barrier layer that extends between the top surface of the first conductive line and the bottom surface of the second conductive line and electrically connecting the first and second conductive lines.

### Claim 6 (depends on 1)

The microelectronic device of claim 1 wherein a top surface of the first conductive line is congruent to a bottom surface of the second conductive line.

### Claim 7 (depends on 1)

The microelectronic device of claim 1:
wherein the first conductive line comprises a plurality of first conductive line segments including at least one first gap therebetween,
wherein the second conductive line comprises a plurality of second conductive line segments including at least one second gap therebetween, and
wherein the at least one first gap is laterally offset from the at least one second gap.

### Claim 8 (depends on 7)

The microelectronic device of claim 7, wherein the first conductive line segments, the second conductive line segments and the first and second gaps are arranged in a brick wall pattern so as not to fail by electromigration effects.

### Claim 9 (depends on 7)

The microelectronic device of claim 7:
wherein the dual-damascene interconnect structure further comprises a first barrier layer that extends on a bottom surface of the conductive via, on a sidewall of the conductive via, on bottom surfaces of the first conductive line segments outside the conductive via and on sidewalls of the first conductive line segments, and
wherein the single-damascene line structure further comprises a second barrier layer that extends between top surfaces of the first conductive line segments and bottom surfaces of the second conductive line segments and on sidewalls of the second conductive line segments.

### Claim 10 (depends on 1)

The microelectronic device of claim 1 wherein the first and second conductive lines are sufficiently short so as to not fail by electromigration effects.

### Claim 11 (depends on 1)

The microelectronic device of claim 1 wherein the single-damascene line structure is a first single-damascene line structure, the microelectronic device further comprising:
a second single-damascene line structure directly on the first single-damascene line structure opposite the dual-damascene interconnect structure, the second single-damascene line structure comprising a third conductive line on the second conductive line opposite the first conductive line.

### Claim 12

A microelectronic device comprising:
a microelectronic substrate;
a first conductive line on the microelectronic substrate, the first conductive line comprising a plurality of first conductive line segments including at least one first gap therebetween; and
a second conductive line directly on the first conductive line opposite the microelectronic substrate, the second conductive line comprising a plurality of second conductive line segments including at least one second gap therebetween;
wherein the at least one first gap is laterally offset from the at least one second gap.

### Claim 13 (depends on 12)

The microelectronic device of claim 12 wherein the first and second conductive lines are damascene conductive lines.

### Claim 14 (depends on 12)

The microelectronic device of claim 12 wherein each of the first and second conductive line segments is sufficiently short so as to not fail by electromigration effects.

### Claim 15 (depends on 12)

The microelectronic device of claim 12:
wherein the first conductive line comprises a first barrier layer that extends on bottom surfaces of the first conductive line segments and on sidewalls of the first conductive line segments, and
wherein the second conductive line comprises a second barrier layer that extends on bottom surfaces of the second conductive line segments and on sidewalls of the second conductive line segments.

### Claim 16 (depends on 12)

The microelectronic device of claim 12 further comprising:
a first intermetal dielectric layer on the microelectronic substrate, wherein the first conductive line segments extend into the first intermetal dielectric layer;
a second intermetal dielectric layer on the first intermetal dielectric layer opposite the substrate, wherein the second conductive line segments extend into the second intermetal dielectric layer; and
a capping layer between the first and second intermetal dielectric layers.

### Claim 17 (depends on 15)

The microelectronic device of claim 15 further comprising:
a first intermetal dielectric layer on the microelectronic substrate, wherein the first conductive line segments extend into the first intermetal dielectric layer;
a second intermetal dielectric layer on the first intermetal dielectric layer opposite the substrate, wherein the second conductive line segments extend into the second intermetal dielectric layer; and
a capping layer between the first and second intermetal dielectric layers, the capping layer being coplanar with the second barrier layer that extends on bottom surfaces of the second conductive line segments and electrically connecting the first and second conductive lines.

### Claim 18

A microelectronic device comprising:
a damascene structure; and
a single-damascene line structure directly on the damascene structure,
wherein the damascene structure and the single-damascene line structure each comprise a plurality of line segments that are arranged in a brick wall pattern.

### Claim 19 (depends on 18)

The microelectronic device of claim 18 wherein the damascene structure comprises a dual-damascene interconnect structure or a single-damascene line structure.