Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer
AssigneeKabushiki Kaisha Toshiba
InventorsShinya Watanabe, Kazuyuki Higashi, Taku Kamoto
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Abstract
According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate.
Claims12
A semiconductor integrated circuit wafer, comprising:
- multiple chip areas having integrated circuits provided on one side of a semiconductor substrate;
- dicing lines separating the multiple chip areas from each other in the semiconductor substrate;
- a TEG provided in the dicing lines at the one side of the semiconductor substrate;
- first through vias exposed at a back side of the semiconductor substrate in the dicing lines and leading from the back side of the semiconductor substrate through the semiconductor substrate in a thickness direction to the TEG;
- second through vias exposed at the back side of the semiconductor substrate in the chip areas and leading from the back side of the semiconductor substrate through the semiconductor substrate in the thickness direction to the integrated circuits;
- and
- a circuit pattern for indirectly inspecting electrical characteristics of the second through vias provided in the TEG.
A semiconductor integrated circuit wafer, comprising:
- multiple chip areas having integrated circuits provided on one side of a semiconductor substrate;
- dicing lines separating the multiple chip areas from each other in the semiconductor substrate;
- a first mark provided in the dicing lines;
- and
- second marks provided in the dicing lines as through vias, the through vias being exposed at a back side of the semiconductor substrate in the dicing lines and leading from the back side of the semiconductor substrate through the semiconductor substrate in a thickness direction,
- wherein the second marks are different from the first mark in at least one of shape and size along a plane direction of the semiconductor substrate.
Dependencies are inferred from the claim text.