Method for wafer level reliability
AssigneeMagnaChip Semiconductor, Ltd.
InventorsKyeNam Lee, HyunHo Jang
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Abstract
A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 μm on the semiconductor substrate; and assessing hot carrier injection (HCI) for the PMOS element.
Claims10
A method for ensuring wafer level reliability, the method comprising:
- forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate;
- forming a PMOS element having a channel length of less than 0.13 μm on the semiconductor substrate;
- forming a high voltage NMOS element on a semiconductor substrate;
- assessing substrate hot carrier injection (sub-HCI) for the high voltage NMOS element;
- and
- assessing hot carrier injection (HCI) for the PMOS element.
The method of claim wherein the assessing of the sub-HCI is implemented at a condition of gate and drain voltages satisfying an equation, Vg=Vd=Vop, wherein Vg is gate voltage, Vd is drain voltage, and Vop is operating voltage.
Dependencies are inferred from the claim text.