Method of forming an interconnect structure for a semiconductor device

A method of semiconductor device fabrication, comprising:

• providing a substrate having a dielectric layer formed over the substrate;
• forming a plurality of trenches in the dielectric layer;
• forming a patterning layer over the substrate defining a via pattern in a patterning layer disposed over and within the plurality of trenches;
• after defining the via pattern, forming a spacer material layer in regions of the plurality of trenches underlying openings in the via pattern;
• etching a via hole in the dielectric layer using the spacer material layer and the patterning layer as a masking element;
• after etching the via hole, removing the patterning layer from within the plurality of trenches;
• and
• after removing the patterning layer, filling the via hole and plurality of trenches with a conductive material.

A method, comprising:

• providing a substrate having a plurality of trenches formed in a dielectric layer disposed over the substrate, wherein the trenches provide a routing for an interconnection layer of a semiconductor device;
• forming a patterning layer over the substrate and in the plurality of trenches;
• providing a plurality of openings in the patterning layer, wherein a first opening of the plurality of openings exposes a portion of a first trench of the plurality of trenches, wherein the portion is defined by a sidewall of the first trench and a sidewall of the patterning layer;
• forming a conformal layer of spacer material over the substrate including on sidewall of the portion of the first trench of the plurality of trenches and on sidewalls of a second trench of the plurality of trenches;
• etching the spacer material layer, such that a region of a bottom surface of the second trench of the plurality of trenches is exposed;
• etching a via hole extending from the region of the bottom surface of the second trench into the dielectric layer, wherein a dimension of the via hole is defined by a thickness of the spacer material layer.