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US 9,431,296 B2Granted
Structure and method to form liner silicide with improved contact resistance and reliablity
AssigneeInternational Business Machines Corporation
InventorsVeeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
Life of this patent
Estimating the term…
Abstract
A contact structure with improved contact resistance and reliability is provided by forming an inner spacer between a contact liner and dielectric layers laterally surrounding the contact structure. The inner spacer severs as a barrier to prevent diffusion of metals from the contact liner into the dielectric layers.
Claims20
A method of forming a semiconductor structure comprising:
- forming a plurality of contact openings through at least one contact level dielectric layer and a portion of an interlevel dielectric (ILD) layer, the plurality of contact openings exposing portions of an epitaxial source region and an epitaxial drain region of at least one semiconductor device;
- forming an inner spacer on a sidewall of each of the plurality of contact openings, wherein an entirety of the inner spacer contacts the sidewall of each of the plurality of contact openings;
- forming a contact liner material layer on the inner spacer and bottom surfaces of the plurality of contact openings, wherein bottom portions of the contact liner material layer in the plurality of contact openings react with exposed portions of the epitaxial source region and the epitaxial drain region to form liner silicide portions;
- and
- forming a contact conductor layer to fill remaining volumes of the plurality of contact openings.
2 more elements
A semiconductor structure comprising:
- at least one semiconductor device including a functional gate structure and an epitaxial source region and an epitaxial drain region located on opposite sides of the functional gate structure, the functional gate structure, the epitaxial source region and the epitaxial drain region laterally surrounded by an interlevel dielectric (ILD) layer;
- and
- a plurality of source/drain contact structures extending through at least one contact level dielectric layer and a portion of the ILD layer and in contact with portions of the epitaxial source region and the epitaxial drain region, wherein each of the plurality of source/drain contact structures comprises:
- an inner spacer located on a sidewall of each of a plurality of source/drain contact openings that is laterally surrounded by the at least one contact level dielectric layer and the portion of the ILD layer, wherein an entirety of the inner spacer contacts the sidewall of each of the plurality of contact openings,
- a contact liner having a first portion in contact with the inner spacer and a second portion in contact with the portions of the epitaxial source and drain regions, wherein the second portion of the contact liner is a liner silicide portion formed by a reaction between a material of the first portion of the contact liner and a semiconductor material of the epitaxial source and drain regions, and
- a contact conductor filling in a remaining volume of each of the plurality of source/drain contact openings.
3 more elements
A semiconductor structure comprising:
- a plurality of fin field effect transistors (FinFETs) formed on a substrate, the plurality of FinFETs comprising:
- a first FinFET formed in a first device region of the substrate, the first FinFET comprising:
- a first gate stack formed in a first gate cavity and straddling a channel portion of a first semiconductor fin, wherein the first gate stack includes a first gate dielectric formed on sidewalls and a bottom of the first gate cavity, a first work function material portion formed on the first gate dielectric, and a first gate electrode filling in a remaining volume of the first gate cavity, and first epitaxial source and drain regions located on opposite sides of the first gate stack;
- and a second FinFET formed in a second device region of the substrate, the second FinFET comprising:
- a second gate stack formed in a second gate cavity and straddling a channel portion of a second semiconductor fin, wherein the second gate stack includes a second gate dielectric formed on sidewalls and a bottom of the second gate cavity, a second work function material portion formed on the second gate dielectric, and a second gate electrode filling in a remaining volume of the second gate cavity, and second epitaxial source and drain regions located on opposite sides of the second gate stack;
- and a plurality of source/drain contact structures extending through at least one contact level dielectric layer and a portion of an interlevel dielectric (ILD) layer and in contact with portions of the first epitaxial source and drain regions and the second epitaxial source and drain regions, wherein each of the plurality of source/drain contact structures comprises:
- an inner spacer located on a sidewall of each of a plurality of source/drain contact openings that is laterally surrounded by the at least one contact level dielectric layer and the portion of the ILD layer, wherein an entirety of the inner spacer contacts the sidewall of each of the plurality of contact openings, a contact liner having a first portion in contact with the inner spacer and a second portion in contact with the portions of the epitaxial source and drain regions, and a contact conductor filling in a remaining volume of each of the plurality of source/drain contact openings.
4 more elements
Dependencies are inferred from the claim text.