Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes

A method of forming an integrated circuit comprising:

• providing a patternable structure comprising a first hard mask layer, a first patternable layer underlying the first hard mask layer, an etch stop layer disposed between the first hard mask layer and the first patternable layer, and a second hard mask layer disposed between the etch stop layer and the first patternable layer wherein the second hard mask layer has etch selectivity in an etchant as compared to the first hard mask layer;
• providing mandrels over the first hard mask layer;
• forming sidewall spacers adjacent sidewalls of the mandrels;
• removing the mandrels, with the sidewall spacers remaining and defining gaps therebetween;
• etching the first hard mask layer through the gaps between the sidewall spacers to the etch stop layer with etching terminated at the etch stop layer to form a first patterned hard mask feature and a second patterned hard mask feature;
• selectively modifying a critical dimension of the first patterned hard mask feature relative to the second patterned hard mask feature to form a biased hard mask feature, wherein a space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature;
• and
• selectively etching the second hard mask layer through the exposed surface between the sidewalls of the biased hard mask feature and the second patterned hard mask feature at a higher rate than etching of the biased hard mask feature and the second patterned hard mask feature;
• etching the first patternable layer through exposed material in the space defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature after etching the second hardmask layer through the exposed surface between the sidewalls of the biased hard mask feature and the second patterned hard mask feature.

A multiple critical dimension self-aligned double patterning process comprising:

• providing a patternable structure comprising a first hard mask layer, a first patternable layer underlying the first hard mask layer, and an etch stop layer disposed between the first hard mask layer and the first patternable layer;
• providing mandrels over the first hard mask layer;
• forming sidewall spacers adjacent sidewalls of the mandrels;
• removing the mandrels, with the sidewall spacers remaining and defining gaps therebetween;
• etching the first hard mask layer through the gaps between the sidewall spacers to the etch stop layer with etching terminated at the etch stop layer to form a first patterned hard mask feature and a second patterned hard mask feature;
• selectively modifying a critical dimension thickness of the first patterned hard mask feature relative to the second patterned hard mask feature to form a biased hard mask feature, wherein a space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature;
• and
• etching the first patternable layer through exposed material in the space defined between the sidewalls of the biased hard mask feature and the second patterned hard mask feature.