Salicided structure to integrate a flash memory device with a high κ, metal gate logic device

An integrated circuit for an embedded flash memory device, said integrated circuit comprising:

• a semiconductor substrate including a memory region and a logic region adjacent to the memory region, the memory region including a common source/drain region and a pair of individual source/drain regions arranged on opposite sides of the common source/drain region;
• a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9;
• and
• a pair of flash memory cell devices arranged over the memory region, wherein each flash memory cell device corresponds to one of the individual source/drain regions and includes:
• a select gate and a memory gate arranged between the common source/drain region and the corresponding individual source/drain region;
• a charge trapping dielectric arranged between neighboring sidewalls of the memory and select gates, and arranged under the memory gate;
• and
• a silicide contact pad arranged over a top surface of the memory gate, wherein a top surface of the silicide contact pad is recessed relative to top surfaces of the charge trapping dielectric, the select gate, and the metal gate.

An integrated circuit comprising:

• a logic device arranged on a semiconductor substrate, wherein the logic device comprises a metal gate arranged over and spaced from the semiconductor substrate;
• a memory cell device arranged on the semiconductor substrate and laterally spaced from the logic device, wherein the memory cell device includes a first memory cell gate laterally spaced from a second memory cell gate;
• and
• a silicide contact pad arranged on a top surface of the first memory cell gate and recessed below substantially coplanar top surfaces of the metal and second memory cell gates.