One-time programmable memory and method for making the same
AssigneeKilopass Technology, Inc.
InventorHarry Shengwen Luan
Life of this patent
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Abstract
A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology.
Claims17
A method of manufacturing a one-time programmable non-volatile memory cell comprising:
- forming a buried bitline in a substrate, the buried bitline of a first conductivity type;
- forming a dielectric layer over at least a portion of the buried bitline;
- forming a polysilicon gate layer over at least a portion of the dielectric layer;
- doping the polysilicon gate layer to cause the polysilicon gate layer to be a second conductivity type;
- and
- after the doping, etching the polysilicon gate layer to form a conductive gate over the dielectric layer, the conductive gate formed over a channel region under the conductive gate and dielectric layer.
A method of manufacturing an array of one-time programmable non-volatile memory cells, comprising:
- forming a plurality of parallel buried bitlines in a substrate, each buried bitline of a first conductivity type, such that the buried bitline has a graded dopant concentration with a lower dopant concentration near the substrate surface and a higher dopant concentration deeper in the substrate;
- forming a dielectric layer over at least a portion of the buried bitlines;
- and
- forming a plurality of parallel metal gates over at least portions of the dielectric layer, each metal gate perpendicular to the buried bitlines and formed over a channel region under the metal gate and a portion of dielectric layer.
A method of manufacturing an array of one-time programmable non-volatile memory cells, comprising:
- forming a plurality of buried bitlines in a substrate, each buried bitline having a deep layer of a first conductivity type and a shallow layer of second conductivity type;
- forming a dielectric layer over at least a portion of the buried bitlines;
- and
- forming a plurality of parallel metal gates over at least a portion of the dielectric layer, each metal gate perpendicular to the buried bitlines and formed over a channel region under the metal gate and dielectric layer.
A method of manufacturing an array of one-time programmable non-volatile memory cells, the manufacturing method having a minimum feature size of F, comprising:
- forming a plurality of buried bitlines of a first conductivity type in a substrate, each buried bitline having a defined width no more than F;
- forming a dielectric layer over at least a portion of the buried bitlines;
- and
- forming a plurality of metal gates over at least a portion of the dielectric layer, each metal gate perpendicular to the buried bitlines and having a defined width no more than F, the metal gate formed over a channel region under the metal gate and dielectric layer.
Dependencies are inferred from the claim text.