Edge termination for super junction MOSFET devices
AssigneeVishay-Siliconix
InventorDeva N. Pattanayak
Life of this patent
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Abstract
In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N− type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.
Claims20
A Super Junction metal oxide semiconductor field effect transistor (MOSFET) device comprising:
- a substrate;
- a charge compensation region located above said substrate and comprising a plurality of columns of P type dopant within an N type dopant region;
- an N− type dopant layer located above said charge compensation region;
- a source, a portion of said source is located above said N− type dopant layer;
- a drain, a portion of said drain is located above said N− type dopant layer;
- and
- an edge termination structure located between said source and said drain, a portion of said edge termination structure is located above said N− type dopant layer;
- said plurality of columns of P type dopant are similar in height beneath said source, said edge termination structure, and said drain.
A Super Junction metal oxide semiconductor field effect transistor (MOSFET) device comprising:
- a substrate;
- a charge compensation region located above said substrate and comprising a plurality of columns of N type dopant within a P type dopant region;
- a P− type dopant layer located above said charge compensation region;
- a source, a portion of said source is located above said P− type dopant layer;
- a drain, a portion of said drain is located above said P− type dopant layer;
- and
- an edge termination structure located between said source and said drain, a portion of said edge termination structure is located above said P− type dopant layer;
- said plurality of columns of N type dopant are similar in height beneath said source, said edge termination structure, and said drain.
A method comprising:
- generating a charge compensation region of a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device, wherein said charge compensation region is located above a substrate and comprising a plurality of columns of first type dopant within a second type dopant region, said Super Junction MOSFET device comprises a source and a drain;
- generating a layer located above said charge compensation region and comprising a second type dopant having a lower concentration than said second type dopant region, a portion of said source is located above said layer, a portion of said drain is located above said layer;
- and
- generating an edge termination structure located between said source and said drain, a portion of said edge termination structure is located above said layer;
- said plurality of columns of first type dopant are similar in height beneath said source, said edge termination structure, and said drain.
Dependencies are inferred from the claim text.