Data managing method, memory control circuit unit and memory storage apparatus

A memory control circuit unit, for controlling a rewritable non-volatile memory module, the memory control circuit unit comprises:

• a host interface configured to couple to a host system;
• a memory interface configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units;
• and
• a memory managing circuit, coupled to the host interface and the memory interface, and configured to configures a plurality of logic units for mapping to at least a part of the physical erasing units,
• wherein the memory managing circuit receives a first reading command from the host system, wherein the first reading command indicates to read data from a first logic unit among the logic units, and the first logic unit is mapped to a first physical erasing unit among the physical erasing units,
• wherein the memory managing circuit sends a command sequence to read a first data stream from the first physical erasing unit, wherein the first data stream comprises first user data, a first error detecting code and a first error correcting code,
• wherein the memory managing circuit performs a first decoding procedure by using the first error detecting code, the first error correcting code and the first user data, and in the first decoding procedure, wherein the memory managing circuit performs an error correcting code syndrome calculation on the first data stream to generate a first syndrome corresponding to the first data stream, and performs a cyclic redundancy check calculation on the first user data to generate a second error detecting code corresponding to the first user data, generates a first error locator polynomial corresponding to the first data stream according to the first syndrome and calculates a first error bit number of the first data stream, obtains the first error bit location corresponding to the first user data according to the first syndrome, the first error locator polynomial and an error location searching rule, performs the cyclic redundancy check calculation on the first error bit location to generate a third error detecting code corresponding to the first error bit location, performs an XOR logic operation on the third error detecting code and the second error detecting code to generate a fourth error detecting code, and determines whether the fourth error detecting code is equal to the first error detecting code,
• wherein the memory managing circuit stops the first decoding procedure if the fourth error detecting code is equal to the first error detecting code, and corrects the first user data to obtain the corrected user data by using the first error bit location checking whether the first data stream is correctable, and transmits the corrected user data to the host system, and identifies that the first user data is successfully decoded,
• wherein the memory managing circuit outputs an error message to the host system if the fourth error detecting code is not equal to the first error detecting code, and
• wherein if the first user data is successfully decoded, the memory managing circuit transmits corrected user data obtained by successfully decoding the first user data to the host system in response to the first reading command.

A memory storage apparatus, comprising:

• a connection interface unit configured to couple to a host system;
• a rewritable non-volatile memory module, having a plurality of physical erasing units;
• and
• a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, and is configured to configure a plurality of logic units for mapping to at least a part of the physical erasing units,
• wherein the memory control circuit unit receives a first reading command from the host system, wherein the first reading command indicates to read data from a first logic unit among the logic units, and the first logic unit is mapped to a first physical erasing unit among the physical erasing units,
• the memory control circuit unit reads a first data stream from the first physical erasing unit, wherein the first data stream comprises first user data, a first error detecting code and a first error correcting code,
• wherein the memory control circuit unit performs a first decoding procedure by using the first error detecting code, the first error correcting code and the first user data, and in the first decoding procedure, the memory control circuit unit performs an error correcting code syndrome calculation on the first data stream to generate a first syndrome corresponding to the first data stream, performs a cyclic redundancy check calculation on the first user data to generate a second error detecting code corresponding to the first user data, generates a first error locator polynomial corresponding to the first data stream according to the first syndrome, calculates a first error bit number of the first data stream, obtains the first error bit location corresponding to the first user data according to the first syndrome, the first error locator polynomial and an error location searching rule, performs the cyclic redundancy check calculation on the first error bit location to generate a third error detecting code corresponding to the first error bit location, performs an XOR logic operation on the third error detecting code and the second error detecting code to generate a fourth error detecting code, and determines whether the fourth error detecting code is equal to the first error detecting code,
• wherein the memory control circuit unit stops the first decoding procedure if the fourth error detecting code is equal to the first error detecting code, and corrects the first user data to obtain the corrected user data by using the first error bit location without checking whether the first data stream is correctable, and transmits the corrected user data to the host system, and identifies that the first user data is successfully decoded,
• wherein the memory control circuit unit outputs an error message to the host system if the fourth error detecting code is not equal to the first error detecting code, and
• wherein if the first user data is successfully decoded, the memory control circuit unit transmits corrected user data obtained by successfully decoding the first user data to the host system in response to the first reading command.