Non-volatile memory program algorithm device and method

A method of programming a memory device having memory cells each including source and drain regions in a semiconductor substrate with a channel region therebetween, a floating gate disposed over and affecting a conductivity of at least a portion of the channel region, and one or more additional conductive gates insulated from the floating gate and the substrate, wherein each memory cell is programmable by applying programming voltages to the source region and the one or more additional conductive gates to cause electrons originating from the drain region to be injected onto the floating gate, and wherein a program state of each memory cell is readable by applying a voltage differential between the source and the drain regions and measuring a read current in the channel region, the method comprising:

• for each of a first subset of a plurality of the memory cells:
• 1) applying a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 2) reading a program state of the memory cell, and
• 3) repeating steps 1 and 2 until the memory cell exhibits a read current in step 2 which reaches a first threshold value, wherein the repeating of steps 1 and 2 includes increasing at least one of the programming voltages of step 1 by a first step value each time step 1 is repeated;
• and
• for each of a second subset of the plurality of memory cells:
• 4) applying a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 5) reading a program state of the memory cell, and
• 6) repeating steps 4 and 5 until the memory cell exhibits a read current in step 5 which reaches a second threshold value different from the first threshold value, wherein the repeating of steps 4 and 5 includes increasing at least one of the programming voltages of step 4 by a second step value each time step 4 is repeated.

A method of programming a memory device having memory cells each including source and drain regions in a semiconductor substrate with a channel region therebetween, a floating gate disposed over and affecting a conductivity of at least a portion of the channel region, and one or more additional conductive gates insulated from the floating gate and the substrate, wherein each memory cell is programmable by applying programming voltages to the source region and the one or more additional conductive gates to cause electrons originating from the drain region to be injected onto the floating gate, and wherein a program state of each memory cell is readable by applying a voltage differential between the source and the drain regions and measuring a read current in the channel region, the method comprising:

• for each of a plurality of the memory cells:
• 1) applying a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 2) reading a program state of the memory cell, and
• 3) repeating steps 1 and 2 until the memory cell exhibits a read current in step 2 which reaches a first threshold value, wherein the repeating of steps 1 and 2 includes increasing at least one of the programming voltages of step 1 by a first step value each time step 1 is repeated;
• and
• after the first threshold value is reached for all the plurality of memory cells, applying a kicker pulse of programming voltages to the source regions and the one or more conductive gates for all the plurality of the memory cells, wherein the applying of the kicker pulse includes increasing at least one of the programming voltages by a second step value relative to the programming voltages applied in steps 1-3.

A memory device, comprising:

• memory cells each including:
• source and drain regions in a semiconductor substrate with a channel region therebetween,
• a floating gate disposed over and affecting a conductivity of at least a portion of the channel region,
• one or more additional conductive gates insulated from the floating gate and the substrate,
• wherein each memory cell is configured to be programmable by applying programming voltages to the source region and the one or more additional conductive gates to cause electrons originating from the drain region to be injected onto the floating gate, and wherein a program state of each memory cell is readable by applying a voltage differential between the source and the drain regions and measuring a read current in the channel region;
• control circuitry configured to:
• 1) apply a pulse of programming voltages to the source regions and the one or more conductive gates for a plurality of the memory cells,
• 2) read program states of the plurality of memory cells, and
• 3) repeat steps 1 and 2 until at least one of the plurality of memory cells exhibits a read current in step 2 which reaches a first threshold value, wherein the repeat of steps 1 and 2 includes increasing at least one of the programming voltages of step 1 by a first step value each time step 1 is repeated;
• after the first threshold value has been reached, for each of a first subset of the plurality of memory cells:
• 4) apply a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 5) read a program state of the memory cell, and
• 6) repeat steps 4 and 5 until the memory cell exhibits a read current in step 5 which reaches a second threshold value different from the first threshold value, wherein the repeat of steps 4 and 5 includes increasing at least one of the programming voltages of step 4 by a second step value each time step 4 is repeated, wherein the second step value is less than the first step value;
• and
• after the first threshold value has been reached, for each of a second subset of the plurality of memory cells:
• 7) apply a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 8) read a program state of the memory cell, and
• 9) repeat steps 7 and 8 until the memory cell exhibits a read current in step 8 which reaches a third threshold value different from the first and second threshold values, wherein the repeat of steps 7 and 8 includes increasing at least one of the programming voltages of step 7 by a third step value each time step 7 is repeated, wherein the third step value is less than the first step value.

A memory device comprising:

• memory cells each including:
• source and drain regions in a semiconductor substrate with a channel region therebetween,
• a floating gate disposed over and affecting a conductivity of at least a portion of the channel region,
• one or more additional conductive gates insulated from the floating gate and the substrate,
• wherein each memory cell is configured to be programmable by applying programming voltages to the source region and the one or more additional conductive gates to cause electrons originating from the drain region to be injected onto the floating gate, and wherein a program state of each memory cell is readable by applying a voltage differential between the source and the drain regions and measuring a read current in the channel region;
• control circuitry configured to:
• for each of a first subset of a plurality of the memory cells:
• 1) apply a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 2) read a program state of the memory cell, and
• 3) repeat steps 1 and 2 until the memory cell exhibits a read current in step 2 which reaches a first threshold value, wherein the repeat of steps 1 and 2 includes increasing at least one of the programming voltages of step 1 by a first step value each time step 1 is repeated;
• and
• for each of a second subset of the plurality of memory cells:
• 4) apply a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 5) read a program state of the memory cell, and
• 6) repeat steps 4 and 5 until the memory cell exhibits a read current in step 5 which reaches a second threshold value different from the first threshold value, wherein the repeat of steps 4 and 5 includes increasing at least one of the programming voltages of step 4 by a second step value each time step 4 is repeated.

A memory device comprising:

• memory cells each including:
• source and drain regions in a semiconductor substrate with a channel region therebetween,
• a floating gate disposed over and affecting a conductivity of at least a portion of the channel region,
• one or more additional conductive gates insulated from the floating gate and the substrate,
• wherein each memory cell is configured to be programmable by applying programming voltages to the source region and the one or more additional conductive gates to cause electrons originating from the drain region to be injected onto the floating gate, and wherein a program state of each memory cell is readable by applying a voltage differential between the source and the drain regions and measuring a read current in the channel region;
• control circuitry configured to:
• for each of a plurality of the memory cells:
• 1) apply a pulse of programming voltages to the source region and the one or more conductive gates of the memory cell,
• 2) read a program state of the memory cell, and
• 3) repeat steps 1 and 2 until the memory cell exhibits a read current in step 2 which reaches a first threshold value, wherein the repeat of steps 1 and 2 includes increasing at least one of the programming voltages of step 1 by a first step value each time step 1 is repeated;
• and
• after the first threshold value is reached for all the plurality of memory cells, apply a kicker pulse of programming voltages to the source regions and the one or more conductive gates for all the plurality of the memory cells, wherein the applying of the kicker pulse includes increasing at least one of the programming voltages by a second step value relative to the programming voltages applied in steps 1-3.