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US 9,431,125 B2Granted
Method and system for adaptive setting of verify levels in flash memory
AssigneeSanDisk Technologies LLC
InventorsIdan Alrod, Eran Sharon, Noam Presman, Ilya Bekkerman
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Abstract
A system and method for computing MLC flash memory cell programming parameters to dynamically adjust verify voltage levels is provided. The method may use an iterative guess and check process that will result in a distribution of states, specifically a cell voltage distribution (CVD) that minimizes the cell error rate in cells encoded in interleaved error correction code (ECC) mode, and that balances the bit error rate between pages in cells encoded in non-interleaved ECC mode.
Claims13
A method for adaptively setting write verify levels in a memory, the method comprising:
- in a controller of the memory, the controller:
- in response to detecting a verify level trigger event,
- determining a cell voltage distribution (CVD) for each of a plurality of states of multi-level cell (MLC) memory cells in a group of the MLC memory cells in the memory;
- based on the determined CVD, adjusting a write verify level for a portion of the plurality of states, wherein the portion of the plurality of states comprises all of the plurality of states except for a lowest voltage state and a highest voltage state in the group of the MLC memory cells;
- and
- wherein adjusting the write verify level for the portion of the plurality of states comprises:
- sequentially moving the verify level of each of the portion of the plurality of states to achieve a target CVD overlap area, respectively, between each adjacent state;
- wherein when the group of the MLC memory cells comprises MLC memory cells programmed in an interleaved ECC mode, the target CVD overlap area comprises an equal CVD overlap area between each adjacent state;
- and
- wherein when the group of the MLC memory cells comprises MLC memory cells programmed in a non-interleaved ECC mode, the target CVD overlap area between a first two adjacent states differs from a predetermined size of a second CVD overlap area between a second two adjacent states.
7 more elements
A memory device comprising:
- a non-volatile memory having multi-level cell (MLC) memory cells;
- and
- a controller in communication with the non-volatile memory, wherein the controller is configured to:
- in response to detection of a verify level trigger event
- determine a cell voltage distribution (CVD) for each of a plurality of states of multi-level cell (MLC) memory cells in a group of the MLC memory cells;
- based on the determined CVD, adjust a write verify level for a portion of the plurality of states to achieve a desired error probability distribution between all states in the group of the MLC memory cells of the non-volatile memory device, wherein the portion of the plurality of states comprises all of the plurality of states except for a lowest voltage state and a highest voltage state in the group of the MLC memory cells;
- wherein to adjust the write verify level for the portion of the plurality of states, the controller is further configured to:
- sequentially move the verify level of each of the portion of the plurality of states to achieve a target CVD overlap area, respectively, between each adjacent state;
- wherein, when the group of the MLC memory cells comprises MLC memory cells programmed in an interleaved ECC mode, the target CVD overlap area comprises an equal CVD overlap area between each adjacent state;
- and
- wherein when the group of the MLC memory cells comprises MLC memory cells programmed in a non-interleaved ECC mode, the target CVD overlap area between a first two adjacent states differs from a predetermined size of a second CVD overlap area between a second two adjacent states.
8 more elements
Dependencies are inferred from the claim text.