Method to reduce program disturbs in non-volatile memory cells

A memory circuit, comprising:

• a memory array including memory cells arranged in rows and columns, wherein each memory cell includes a non-volatile memory (NVM) transistor coupled to an insulated-gate field-effect transistor (IGFET), wherein gates of the NVM transistors of memory cells in a same row couple to and share a global wordline and one end of memory cells in a same column couple to and share a bitline;
• and
• a programmable circuitry configured to select a first memory cell which is in a first row and a first column for programming, the programmable circuitry further configured to provide a first high voltage (HV) to a first global wordline associated with the first row and a second HV to a first bitline associated with the first column, wherein a bias is applied to the NVM transistor in the first memory cell for the programming, the programmable circuitry further configured to provide a third voltage which includes a magnitude that is less than the second HV to a second global wordline associated with a second row and an inhibit voltage (VINT) to a second bitline associated with a second column to reduce a bias applied to a NVM transistor in an unselected memory cell, and wherein the first HV includes a higher voltage magnitude than the second HV.

A memory array, comprising:

• a plurality of memory cells arranged in rows and columns, wherein each memory cell includes a non-volatile memory (NVM) transistor, wherein memory cells in a same row share a global wordline and memory cells in a same column share a bitline,
• wherein during programming of a first memory cell associated with a first row and a first column, a positive voltage is applied to a first global wordline associated with the first row and a negative voltage is applied to a first bit line associated with the first column to apply a bias to a NVM transistor in the first memory cell, while a negative marginal voltage, which has a magnitude that is less than the negative voltage, is applied to a second global wordline associated with an unselected second row for programming, and an inhibited voltage is applied to a second bitline associated with an unselected second column for programming to reduce a bias applied to memory cells in the unselected second row and column for programming.