Semiconductor memory device including strings including memory cell transistors

A memory system comprising:

• a memory comprising first strings coupled to respective bit lines and second strings respectively coupled to the bit lines, wherein
• each of the first and second strings comprises memory cell transistors coupled in series;
• the first strings configure a first string group;
• the second strings configure a second string group;
• in each string group, a set of memory cell transistors each from each string configures a unit;
• and
• a controller configured to:
• sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong;
• sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong after the write in the first string group;
• and
• sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong after the write in the second string group, wherein
• the first units of the first string group are different from the second units.