Column address decoding

An electronic system comprising:

• supervisory circuitry to generate a memory access;
• and
• at least one memory coupled to the supervisory circuitry, the at least one memory comprising:
• an even buffer to temporarily store data from an even memory array;
• an odd buffer, separate and distinct from the even buffer, to temporarily store data from an odd memory array;
• a clock circuit to generate alternating even clock periods and odd clock periods;
• an address circuit to generate an even address that changes in the even clock periods and an odd address that changes in the odd clock periods;
• even decode circuitry to decode the even address;
• odd decode circuitry, separate and distinct from the even decode circuitry, to decode the odd address;
• even selection circuitry to select one or more cells of the even buffer during the odd clock periods based, at least in part, on the decoded even address to access the temporarily stored data in the even buffer;
• odd selection circuitry, separate and distinct from the even selection circuitry, to select one or more cells of the odd buffer during the even clock periods based, at least in part, on the decoded odd address to access the temporarily stored data in the odd buffer;
• even remap circuitry coupled between the address circuit and the even decode circuit;
• and
• odd remap circuitry, separate and distinct from the even buffer, coupled between the address circuit and the odd decode circuit;
• wherein the odd address is already provided at an output of the address circuit at a start of the odd clock period to be decoded during the odd clock period after the data for the even address is latched into the even buffer.