Integrated structure comprising neighboring transistors

A memory device comprising:

• a memory plane containing rows and columns of memory cells, each memory cell including an SRAM elementary memory cell and a nonvolatile elementary memory cell coupled together;
• and
• a controller configured to manage the memory plane;
• wherein each nonvolatile elementary memory cell comprises a floating-gate transistor;
• and
• wherein each SRAM elementary memory cell comprises an integrated structure comprising:
• a first MOS transistor comprising a first controllable gate region overlying a first gate dielectric and a first source/drain region,
• a second MOS transistor neighboring the first MOS transistor and comprising a second controllable gate region overlying the first gate dielectric and a second source/drain region, the first controllable gate region coupled to the second source/drain region and the second controllable gate region being coupled to the first source/drain region;
• and
• a first filter capacitor coupled between the first controllable gate region and a reference voltage node and a second filter capacitor coupled between the second controllable gate region and the reference voltage node, the first and the second filter capacitors being formed in a capacitor structure comprising a common conductive region overlying the first and second controllable gate regions and separated therefrom by a second gate dielectric, the common conductive region comprising a continuous element located over a portion of the first and second controllable gate regions and a branch extending downward from the continuous element as far as the first gate dielectric, the branch located between the first and second gate controllable regions and spaced from both the first and second controllable gate regions.

A memory device comprising:

• a memory plane containing rows and columns of memory cells, each memory cell including an SRAM elementary memory cell and a nonvolatile elementary memory cell coupled together;
• and
• a controller configured to manage the memory plane;
• wherein each nonvolatile elementary memory cell comprises a floating-gate transistor;
• and
• wherein each SRAM elementary memory cell and/or the controller comprises an integrated structure comprising a first MOS transistor comprising a first controllable gate region overlying a first gate dielectric, a second MOS transistor neighboring the first MOS transistor and comprising a second controllable gate region overlying the first gate dielectric, and a common conductive region overlying the first and second gate regions and separated therefrom by a second gate dielectric, the common conductive region comprising a continuous element located over a portion of the first and second controllable gate regions and a branch extending downward from the continuous element as far as the first gate dielectric, the branch located between the first and second controllable gate regions, wherein each memory cell comprises a single nonvolatile elementary memory cell coupled between a supply terminal and the SRAM elementary memory cell, the floating-gate transistor of the nonvolatile elementary memory cell being controllable to be turned off when a data item stored in the SRAM elementary memory cell is programmed into the nonvolatile elementary memory cell.

A memory device comprising:

• a memory plane containing rows and columns of memory cells, each memory cell including an SRAM elementary memory cell and a nonvolatile elementary memory cell coupled together;
• and
• a controller configured to manage the memory plane;
• wherein each nonvolatile elementary memory cell comprises a floating-gate transistor;
• and
• wherein each SRAM elementary memory cell and/or the controller comprises an integrated structure comprising a first MOS transistor comprising a first controllable gate region overlying a first gate dielectric, a second MOS transistor neighboring the first MOS transistor and comprising a second controllable gate region overlying the first gate dielectric, and a common conductive region overlying the first and second gate regions and separated therefrom by a second gate dielectric, the common conductive region comprising a continuous element located over a portion of the first and second controllable gate regions and a branch extending downward from the continuous element as far as the first gate dielectric, the branch located between the first and second controllable gate regions, wherein each memory cell comprises two nonvolatile elementary memory cells that each include a floating-gate transistor, the floating-gate transistors having a first conduction electrode connected to a supply terminal and a control electrode coupled to a first control line, second conduction electrodes of the floating-gate transistors of the nonvolatile elementary memory cells being respectively coupled to outputs of two inverters of the SRAM elementary memory cell by way of a controllable interconnect stage, the floating-gate transistors being controllable to be turned off when a data item stored in the SRAM elementary memory cell is programmed into the nonvolatile elementary memory cells.