US 9,431,098 B1 · Structure for reducing pre-charge voltage for static random-access memory arrays · patentgrep

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Abstract

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Claims10

Dependent claims

A memory cell arrangement of Static Random-Access Memory (SRAM) cells comprising:

one or more SRAM cell groups,
wherein each of the one or more SRAM cell groups includes two or more SRAM cells that are connected to an input of a local read amplifier by at least one common local bit-line, and
wherein outputs of the local read amplifiers are connected to a shared global bit-line, the shared global bit-line being connected to a pre-charge circuit that is adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data, the pre-charge circuit including a limiter circuit comprising:
a pre-charge regulator circuit connected to the shared global bit-line to pre-charge the shared global bit-line with the programmable pre-charge voltage;
and
an evaluation and translation circuit connected to the pre-charge regulator circuit and the shared global bit-line to compensate for leakage current of the shared global bit-line without changing a voltage level of the global bit-line,
wherein the pre-charge regulator circuit comprises:
a 1st p-FET connected with its source to a power supply voltage and its drain to a first terminal of a pre-charge switch which is connected with its second terminal to the shared global bit-line;
and
a 1st n-FET which is connected with its source to the first terminal of the pre-charge switch, wherein a drain of the 1st n-FET is connected to a gate of the 1st p-FET as well as to a first terminal of a first programmable resistor which is connected with its second terminal to the power supply voltage,
wherein a gate of the 1st n-FET is connected to a reference voltage (Vref) signal.

8 more elements

A memory cell arrangement of Static Random-Access Memory (SRAM) cells comprising:

one or more SRAM cell groups,
wherein each of the one or more SRAM cell groups includes two or more SRAM cells that are connected to an input of a local read amplifier by at least one common local bit-line, and
wherein outputs of the local read amplifiers are connected to a shared global bit-line, the shared global bit-line being connected to a pre-charge circuit that is adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data, the pre-charge circuit including a limiter circuit comprising:
a pre-charge regulator circuit connected to the shared global bit-line to pre-charge the shared global bit-line with the programmable pre-charge voltage;
and
an evaluation and translation circuit connected to the pre-charge regulator circuit and the shared global bit-line to compensate for leakage current of the shared global bit-line without changing a voltage level of the global bit-line,
wherein the pre-charge regulator circuit comprises:
a 1st p-FET connected with its drain to the shared global bit-line and its source to a power supply voltage, wherein a gate of the 1st p-FET is connected to a drain of a 2nd p-FET, a source of the 2nd p-FET being connected to the power supply voltage;
a 3rd p-FET which is connected with its drain to the gate of the 1st p-FET and with its source is connected to the power supply voltage;
and
a 1st n-FET which is connected with its drain to the gate of the 1st p-FET and with its source to a drain of a 2nd n-FET which is connected with its source to the shared global bit-line, wherein a gate of the 2nd n-FET and a gate of the 2nd p-FET are together connected to a global bit-line pre-charge line, wherein a gate of the 1st n-FET is connected to a Vref signal, and wherein a gate of the 3rd p-FET is connected to a p-bias voltage (Vbias-p) signal.

8 more elements

A memory cell arrangement of Static Random-Access Memory (SRAM) cells comprising:

one or more SRAM cell groups,
wherein each of the one or more SRAM cell groups includes two or more SRAM cells that are connected to an input of a local read amplifier by at least one common local bit-line, and
wherein outputs of the local read amplifiers are connected to a shared global bit-line, the shared global bit-line being connected to a pre-charge circuit that is adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data, the pre-charge circuit including a limiter circuit comprising:
a pre-charge regulator circuit connected to the shared global bit-line to pre-charge the shared global bit-line with the programmable pre-charge voltage;
and
an evaluation and translation circuit connected to the pre-charge regulator circuit and the shared global bit-line to compensate for leakage current of the shared global bit-line without changing a voltage level of the global bit-line, wherein the evaluation and translation circuit comprises:
a 1st n-FET connected with its source to the shared global bit-line and with its drain to a global bit-line out terminal;
a 1st p-FET connected with its drain to the global bit-line out terminal and with its source to a power supply voltage;
and
a 2nd p-FET connected with its source to the power supply voltage, and with its drain to a source of a 3rd p-FET which is connected with its drain to the global bit-line out terminal,
wherein a gate of the 3rd p-FET is connected to a drain of a 4th p-FET which is connected with its source to the power supply voltage,
wherein the gate of the 3rd p-FET is also connected to a drain of a 2nd n-FET which is connected with its source to ground,
wherein a Vref signal is connected to a gate of the 1st n-FET,
wherein a Vbias-p signal is connected to a gate of the 2nd p-FET, and
wherein an inverted signal of the global bit-line pre-charge signal is connected to a gate of the 1st p-FET.

12 more elements

A memory cell arrangement of Static Random-Access Memory (SRAM) cells comprising:

one or more SRAM cell groups,
wherein each of the one or more SRAM cell groups includes two or more SRAM cells that are connected to an input of a local read amplifier by at least one common local bit-line, and
wherein outputs of the local read amplifiers are connected to a shared global bit-line, the shared global bit-line being connected to a pre-charge circuit that is adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data, the pre-charge circuit including a limiter circuit comprising:
a pre-charge regulator circuit connected to the shared global bit-line to pre-charge the shared global bit-line with the programmable pre-charge voltage;
and
an evaluation and translation circuit connected to the pre-charge regulator circuit and the shared global bit-line to compensate for leakage current of the shared global bit-line without changing a voltage level of the global bit-line, wherein the evaluation and translation circuit comprises:
a 1st n-FET which is connected with its source to the shared global bit-line and with its drain to a source of a 2nd n-FET which is connected with its drain to a drain of a 1st p-FET which is connected with its source to a power supply voltage;
a 2nd p-FET which is connected with its source to the power supply voltage and with its drain to the drain of the 1st p-FET;
and
an 3rd p-FET which is connected with its source to the power supply voltage and with its gate to the drain of the 2nd n-FET,
wherein a drain of the 3rd p-FET is connected to a global bit-line out terminal,
wherein a drain of a 3rd n-FET and a drain of an 4th n-FET are connected to the global bit-line out terminal,
wherein a source of the 3rd n-FET and a source of the 4th n-FET are connected to ground,
wherein a Vref signal is connect to a gate of the 9th n FET 2nd n-FET,
wherein a Vbias-p signal is connected to a gate of the 1st p-FET,
wherein an inverted signal of a global bit-line pre-charge signal is connected to a gate of the 2nd p-FET,
wherein the global bit-line pre-charge signal is connected to a gate of the 3rd n-FET, and
wherein a Vbias-n signal is connected to a gate of the 4th n-FET.

15 more elements

A memory cell arrangement of Static Random-Access Memory (SRAM) cells comprising:

one or more SRAM cell groups,
wherein each of the one or more SRAM cell groups includes two or more SRAM cells that are connected to an input of a local read amplifier by at least one common local bit-line, and
wherein outputs of the local read amplifiers are connected to a shared global bit-line, the shared global bit-line being connected to a pre-charge circuit that is adapted for pre-charging the shared global bit-line with a programmable pre-charge voltage before reading data, the pre-charge circuit including a limiter circuit comprising:
a pre-charge regulator circuit connected to the shared global bit-line to pre-charge the shared global bit-line with the programmable pre-charge voltage;
and
an evaluation and translation circuit connected to the pre-charge regulator circuit and the shared global bit-line to compensate for leakage current of the shared global bit-line without changing a voltage level of the global bit-line, wherein the evaluation and translation circuit comprises:
a 1st n-FET which is connected with its source to the shared global bit-line and with its drain to a source of a 2nd n-FET which is connected with its drain to drain of a 1st p-FET which is connected with its source to a power supply voltage;
a 2nd p-FET which is connected with its source to the power supply voltage and with its drain to the drain of the 1st p-FET;
a 3rd p-FET which is connected with its source to the power supply voltage and with its gate to the drain of the 2nd n-FET;
a 3rd n-FET which is connected with its drain to a drain of the 3rd p-FET and with its source to a drain of a 4th n-FET which is connected with its source to ground;
a 5th n-FET which is connected with its drain to the drain of the 3rd p-FET and with is source to ground;
an inverter which is connected with its input to the drain of the 3rd p-FET and with its output to a global bit-line out terminal;
and
a 4th p-FET which is connected with it source to the power supply voltage and with its drain to the drain of the 3rd p-FET, the 4th p-FET being connected with its gate to the global bit-line out terminal,
wherein a gate of the 3rd n-FET is connected to the global bit-line out terminal,
wherein a Vref signal is connected to a gate of the 2nd n-FET,
wherein a Vbias-p signal is connected to a gate of the 1st p-FET,
wherein an inverted signal of a global bit-line pre-charge signal is connected to a gate of the p-FET,
wherein the global bit-line pre-charge signal is connected to a gate of the 5th n-FET, and
wherein a Vbias-n signal is connected to a gate of the 4th n-FET.

17 more elements

Dependencies are inferred from the claim text.