High-density integrated circuit memory
AssigneeXilinx, Inc.
InventorEphrem C. Wu
Life of this patent
Estimating the term…
Abstract
A memory circuit includes an input stage having N input ports and N output ports, wherein N is an integer greater than one. The memory circuit further includes an N:1 port multiplexer coupled to the N output ports of the input stage and configured to time division multiplex the N output ports to one multiplexed port. The memory circuit also includes a random access memory matrix and a 1:N port multiplexer. The memory circuit is coupled to the multiplexed port. The 1:N port multiplexer is coupled to the random access memory matrix and is configured to de-multiplex signals received from the random access memory matrix into N output ports.
Claims18
A memory circuit, comprising:
- an input stage comprising N input ports and N output ports, wherein N is an integer greater than one;
- an N:1 port multiplexer coupled to the N output ports of the input stage and configured to time division multiplex the N output ports to one multiplexed port;
- a random access memory matrix coupled to the multiplexed port;
- and
- a 1:N port multiplexer coupled to the random access memory matrix and comprising N output ports, wherein the 1:N port multiplexer is configured to de-multiplex signals from the random access memory matrix into the N output ports of the 1:N port multiplexer;
- and
- wherein the input stage comprises:
- address decoder circuitry coupled to the N input ports of the input stage;
- wherein the address decoder circuitry is configured to decode a portion of an address for each of the N input ports of the input stage and generate an enable signal for each of the N output ports of the input stage.
A method, comprising:
- receiving memory operations on N input ports, wherein N is an integer greater than one;
- wherein each of the N input ports operates at a first data rate;
- time division multiplexing the memory operations to a single port having a second data rate that is at least N times the first data rate;
- providing the multiplexed memory operations from the single port to a random access memory matrix;
- wherein the random access memory matrix operates at least at the second data rate;
- implementing the memory operations in the random access memory matrix serially;
- comparing a portion of an address for each memory operation received on the N input ports with a port specific identifier;
- and
- deactivating selected ones of the N input ports receiving the memory operations responsive to the comparing.
Dependencies are inferred from the claim text.