US 9,431,094 B1Granted

Input buffer

AssigneeMicron Technology, Inc.

InventorYasuhiro Takai

Life of this patent

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Abstract

Apparatuses including a data input circuit of a semiconductor device are described. An example apparatus includes a first transistor that receives a reference voltage, a second transistor that receives an input signal, cross-couple type transistors, diode-connect type transistors and resistors. The cross-couple type resistors include a third transistor having a gate coupled to a drain of the second transistor, and a fourth transistor having a gate coupled to a drain of the first transistor. The diode-connect type transistors include a fifth transistor having a drain coupled to a drain of the third transistor, and a sixth transistor having a drain coupled to a drain of the fourth transistor. The resistors include a first resistor coupled between a gate and the drain of the fifth transistor and a second resistor coupled between a gate and the drain of the sixth transistor.

Claims20

Dependent claims

An apparatus comprising:

an input node;
a reference node supplied with a reference voltage;
first, second, third and fourth nodes;
a first transistor coupled between the first node and the second node, the first transistor having a gate coupled to the reference node;
a second transistor coupled between the first node and the third node, the second transistor having a gate coupled to the input node;
a third transistor coupled between the second node and the fourth node, the third transistor having a gate coupled to the third node;
a fourth transistor coupled between the third node and the fourth node, the fourth transistor having a gate coupled to the second node;
a first resistor having one end coupled to the second node and further having an other end;
a second resistor having one end coupled to the third node and further having an other end;
a fifth transistor coupled between the second node and the fourth node, the fifth transistor having a gate coupled to an other end of the first resistor;
and
a sixth transistor coupled between the third node and the fourth node, the sixth transistor having a gate coupled to the other end of the second resistor.

9 more elements

An apparatus comprising:

a data input circuit, comprising:
a first transistor having one of a source and a drain coupled to a first output node and configured to receive a reference voltage;
a second transistor having one of a source and a drain coupled to a second output node and configured to receive an input signal;
a third transistor having one of a source and a drain coupled to a power supply and a gate coupled to the second output node;
and
a fourth transistor having one of a source and a drain coupled to the power supply and a gate coupled to the first output node;
a fifth transistor having one of a source and a drain coupled to the power supply and the other of the source and the drain coupled to the first output node;
and
a sixth transistor having one of a source and a drain coupled to the power supply and the other of the source and the drain coupled to the second output node;
and
a first resistor coupled between a gate and the other of the source and the drain of the fifth transistor;
and
a second resistor coupled between a gate and the other of the source and the drain of the sixth transistor,
wherein one of the first resistor and the second resistor is configured to cause a delay in transmitting a potential transition of the other of the source and the drain of the fifth transistor or a potential transition of the other of the source and the drain of the sixth transistor to the gate of the fifth transistor or the gate of the sixth transistor, respectively,
wherein one of the fifth transistor and the sixth transistor remains active in a manner to accelerate the potential transition of a drain of the fifth transistor or the potential transition responsive to the delay by the one of the first resistor and the second resistor, respectively.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/987,355Filed 4 Jan 2016
Granted: 30 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 11/4093
Read-write [R-W] circuits: input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/1084
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input buffers,…
G11C 7/1087
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
G11C 7/1093
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: input synchronization