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US 9,431,093 B2Granted
Semiconductor device and method of driving the same
AssigneeSK hynix Inc.
InventorKyu-Bong Kong
Life of this patent
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Abstract
A semiconductor device includes: a control block suitable for generating a clock control signal in response to a write training signal and a write-related information signal; and an input block suitable for receiving a data signal for a write training mode in response to the clock control signal and a clock signal.
Claims19
A semiconductor device comprising:
- a control block suitable for generating a clock control signal in response to a write training signal and a write-related information signal;
- and
- an input block suitable for receiving a data signal for a write training mode in response to the clock control signal and a clock signal,
- wherein the control block includes:
- a first control unit suitable for generating a write training end signal in response to the write training signal and the write-related information signal;
- and
- a second control unit suitable for generating the clock control signal in response to the write training signal and the write training end signal.
4 more elements
A semiconductor device comprising:
- a first clock control block suitable for generating a first control signal in response to a write training signal and a write-related information signal;
- a second clock control block suitable for generating a second control signal in response to a refresh signal and a precharge signal;
- a third clock control block suitable for generating a clock control signal by selecting one of the first and second control signals in response to the write-related information signal;
- and
- a data input block suitable for receiving a data signal for a write training mode in response to the clock control signal and a clock signal.
2 more elements
A method of driving a semiconductor device capable of entering a write training mode while entering a refresh mode, comprising:
- selecting one of a first control signal corresponding to the write training mode and a second control signal corresponding to the refresh mode by comparing write latency information with section information on a section ranging from when entering the write training mode to when the first control signal is generated;
- generating a clock control signal in response to the first control signal or the second control signal when entering the write training mode or the refresh mode;
- generating a limitation clock signal by defining a toggling section of a clock signal in response to the clock control signal;
- and
- receiving a data signal for the write training mode in response to the limitation clock signal.
2 more elements
Dependencies are inferred from the claim text.