Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.
Claims20
A method of operation of a memory controller device that controls a memory device, the method comprising:
- generating, at the memory controller device, a write strobe having a write-strobe phase;
- receiving, from the memory device, read data accompanied by a read strobe having a read-strobe phase;
- and
- adjusting the write-strobe phase in response to the read-strobe phase.
A memory controller comprising:
- a command interface to send read commands and write commands timed to a clock signal;
- a write circuit to issue write data and a write strobe having a write-strobe phase;
- a read circuit to receive a read data and a read strobe having a read-strobe phase;
- and
- a phase comparator to adjust the write-strobe phase in response to the read-strobe phase.
A memory controller comprising:
- a write circuit to transmit a write strobe having a write-strobe phase;
- a read circuit to receive a read data signal accompanied by a read strobe having a read-strobe phase;
- and
- means for adjusting the write-strobe phase in response to the read-strobe phase.
Dependencies are inferred from the claim text.