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US 9,431,083 B2Granted
Nonvolatile memory device and storage device having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSuk-soo Pyo, Hyuntaek Jung
Life of this patent
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Abstract
A nonvolatile memory device according to the inventive concepts performs a read operation from a true cell storing data and complementary cell storing complementary data, thereby increasing or maximizing sensing margin. Also, the nonvolatile memory device connects a plurality of true cell/complementary cells to a word line, thereby markedly reducing the size of a memory cell array.
Claims15
A nonvolatile memory device comprising:
- first and second true cells storing data;
- first and second complementary cells storing complementary data of the data;
- bit lines respectively connected to first ends of the first and second true cells;
- complementary bit lines respectively connected to first ends of the first and second complementary cells;
- a first sub word line connected to second ends of the first true cells;
- a second sub word line connected to second ends of the second true cells;
- a first complementary sub word line connected to second ends of the first complementary cells;
- a second complementary sub word line connected to second ends of the second complementary cells;
- and
- a first transistor configured to connect the first sub word line to a first source line in response to a first on voltage applied to a first word line;
- a first complementary transistor configured to connect the first complementary sub word line to a first complementary source line in response to the first on voltage;
- a second transistor configured to connect the second sub word line to the first source line in response to a second on voltage applied to a second word line;
- and
- a second complementary transistor configured to connect the second complementary sub word line to the first complementary source line in response to the second on voltage.
11 more elements
A non-volatile memory device, comprising:
- a source line structure;
- a plurality of true memory cells connected between first respective bit lines and a sub word line structure;
- a plurality of complementary memory cells connected between respective complementary bit lines and the sub word line structure;
- a selection structure configured to selectively electrically connect the source line structure to the sub word line structure;
- a control circuit configured to control the selection structure during at least one of a read operation and a write operation such that a first sub word line in the sub word line structure is connected to a first source line in the source line structure and a second sub word line in the sub word line structure is connected to a second source line in the source line structure based on application of an on voltage to a single word line, the first sub word line connected to the plurality of true memory cells, and the second sub word line connected to the plurality of complementary memory cells.
2 more elements
Dependencies are inferred from the claim text.